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Searched refs:UNPREDICTABLE (Results 1 – 25 of 35) sorted by relevance

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/external/apache-commons-bcel/src/main/java/org/apache/bcel/
DConstants.java1279 short UNPREDICTABLE = -2; field
1389 2/*jsr*/, 1/*ret*/, UNPREDICTABLE/*tableswitch*/, UNPREDICTABLE/*lookupswitch*/,
1398 0/*monitorexit*/, UNPREDICTABLE/*wide*/, 3/*multianewarray*/,
1567 UNPREDICTABLE/*putstatic*/, 1/*getfield*/, UNPREDICTABLE/*putfield*/,
1568 UNPREDICTABLE/*invokevirtual*/, UNPREDICTABLE/*invokespecial*/,
1569 UNPREDICTABLE/*invokestatic*/,
1570 …UNPREDICTABLE/*invokeinterface*/, UNPREDICTABLE/*invokedynamic*/, 0/*new*/, 1/*newarray*/, 1/*anew…
1572 1/*monitorexit*/, 0/*wide*/, UNPREDICTABLE/*multianewarray*/, 1/*ifnull*/, 1/*ifnonnull*/,
1586 UNDEFINED, UNPREDICTABLE/*impdep1*/, UNPREDICTABLE/*impdep2*/
1623 0/*dreturn*/, 0/*areturn*/, 0/*return*/, UNPREDICTABLE/*getstatic*/, 0/*putstatic*/,
[all …]
DConst.java1713 public static final short UNPREDICTABLE = -2; field in Const
1887 2/*jsr*/, 1/*ret*/, UNPREDICTABLE/*tableswitch*/, UNPREDICTABLE/*lookupswitch*/,
1896 0/*monitorexit*/, UNPREDICTABLE/*wide*/, 3/*multianewarray*/,
2102 UNPREDICTABLE/*putstatic*/, 1/*getfield*/, UNPREDICTABLE/*putfield*/,
2103 UNPREDICTABLE/*invokevirtual*/, UNPREDICTABLE/*invokespecial*/,
2104 UNPREDICTABLE/*invokestatic*/,
2105 …UNPREDICTABLE/*invokeinterface*/, UNPREDICTABLE/*invokedynamic*/, 0/*new*/, 1/*newarray*/, 1/*anew…
2107 1/*monitorexit*/, 0/*wide*/, UNPREDICTABLE/*multianewarray*/, 1/*ifnull*/, 1/*ifnonnull*/,
2121 UNDEFINED, UNPREDICTABLE/*impdep1*/, UNPREDICTABLE/*impdep2*/
2169 0/*dreturn*/, 0/*areturn*/, 0/*return*/, UNPREDICTABLE/*getstatic*/, 0/*putstatic*/,
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7-xfail.txt9 # Rt == Rt2 is UNPREDICTABLE
21 # if d == n || d == t then UNPREDICTABLE
33 # if d == n || d == t || d == t2 then UNPREDICTABLE
Dinvalid-armv7.txt18 # if d == 15 then UNPREDICTABLE;
122 # if m == 15 then UNPREDICTABLE
144 # if wback && (n == 15 || n == t) then UNPREDICTABLE
178 # The instruction is UNPREDICTABLE, and is not a valid instruction.
196 # The instruction is UNPREDICTABLE, and is not a valid instruction.
221 # if d == 15 then UNPREDICTABLE
265 # if d == 15 || n == 15 then UNPREDICTABLE;
282 # if d == 15 || n == 15 | m == 15 then UNPREDICTABLE
331 # if d == 15 || m == 15 then UNPREDICTABLE;
348 # if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
Dunpredictable-STRBrs-arm.txt9 # if t == 15 then UNPREDICTABLE
Dunpredictable-RSC-arm.txt8 # if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
Dunpredictable-SSAT-arm.txt10 # if d == 15 || n == 15 then UNPREDICTABLE;
Dunpredictable-LSL-regform.txt10 # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
Dunpredictable-UQADD8-arm.txt11 # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
Dinvalid-thumbv7.txt150 # if BitCount(registers) < 1 then UNPREDICTABLE
236 # Rt == Rn is UNPREDICTABLE
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7-xfail.txt9 # Rt == Rt2 is UNPREDICTABLE
21 # if d == n || d == t then UNPREDICTABLE
33 # if d == n || d == t || d == t2 then UNPREDICTABLE
Dinvalid-armv7.txt18 # if d == 15 then UNPREDICTABLE;
122 # if m == 15 then UNPREDICTABLE
144 # if wback && (n == 15 || n == t) then UNPREDICTABLE
162 # if Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;
201 # The instruction is UNPREDICTABLE, and is not a valid instruction.
219 # The instruction is UNPREDICTABLE, and is not a valid instruction.
244 # if d == 15 then UNPREDICTABLE
288 # if d == 15 || n == 15 then UNPREDICTABLE;
305 # if d == 15 || n == 15 | m == 15 then UNPREDICTABLE
354 # if d == 15 || m == 15 then UNPREDICTABLE;
[all …]
Dunpredictable-STRBrs-arm.txt9 # if t == 15 then UNPREDICTABLE
Dunpredictable-RSC-arm.txt8 # if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
Dunpredictable-SSAT-arm.txt10 # if d == 15 || n == 15 then UNPREDICTABLE;
Dunpredictable-LSL-regform.txt10 # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
Dunpredictable-UQADD8-arm.txt11 # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
Dunpredictable-MVN-arm.txt23 # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
Dinvalid-thumbv7.txt150 # if BitCount(registers) < 1 then UNPREDICTABLE
236 # Rt == Rn is UNPREDICTABLE
/external/llvm-project/llvm/test/MC/ARM/
Dunpred-control-flow-in-it-block.s3 @ These instructions all write to the PC, so are UNPREDICTABLE if they are in
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td331 // There is no D31_D0 register as that is always an UNPREDICTABLE encoding.
DARMInstrFormats.td325 // Mask of bits that cause an encoding to be UNPREDICTABLE.
328 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMRegisterInfo.td469 // There is no D31_D0 register as that is always an UNPREDICTABLE encoding.
/external/llvm-project/llvm/lib/Target/ARM/
DARMRegisterInfo.td480 // There is no D31_D0 register as that is always an UNPREDICTABLE encoding.
/external/llvm-project/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp1752 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; in EmulateLDRRtPCRelative()
4434 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; in EmulateLDRRtRnImm()
6358 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; in EmulateLDRImmediateARM()
6496 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; in EmulateLDRRegister()
8686 UNPREDICTABLE; in EmulateRFE()
12667 UNPREDICTABLE; in EmulateSUBSPcLrEtc()

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