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Searched refs:UseTCCInDIV (Results 1 – 13 of 13) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsSubtarget.cpp73 Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM), in MipsSubtarget()
DMipsSubtarget.h143 bool UseTCCInDIV; variable
DMips.td179 "UseTCCInDIV", "false",
DMipsInstrInfo.td217 def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
/external/llvm-project/llvm/lib/Target/Mips/
DMipsSubtarget.cpp82 Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false), in MipsSubtarget()
DMipsSubtarget.h167 bool UseTCCInDIV; variable
DMips.td191 "UseTCCInDIV", "false",
DMipsInstrInfo.td239 def UseTCCInDIV : AssemblerPredicate<(all_of FeatureUseTCCInDIV)>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSubtarget.h164 bool UseTCCInDIV; variable
DMipsSubtarget.cpp82 UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false), in MipsSubtarget()
DMips.td205 "UseTCCInDIV", "false",
DMipsInstrInfo.td239 def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc3849 if (Bits[Mips::FeatureUseTCCInDIV]) UseTCCInDIV = false;