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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonDepArch.h21 enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67 }; enumerator
36 {"generic", Hexagon::ArchEnum::V60},
39 {"hexagonv60", Hexagon::ArchEnum::V60},
DHexagonScheduleV60.td10 // There are four SLOTS (four parallel pipelines) in Hexagon V60 machine.
27 // in the CVI co-processor in the Hexagon V60 machine.
79 // Hexagon V60 Resource Definitions -
DHexagonDepArch.td15 …btargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architec…
DHexagonSubtarget.h153 return getHexagonArchVersion() >= Hexagon::ArchEnum::V60; in hasV60Ops()
156 return getHexagonArchVersion() == Hexagon::ArchEnum::V60; in hasV60OpsOnly()
201 return HexagonHVXVersion >= Hexagon::ArchEnum::V60; in useHVXV60Ops()
DHexagonInstrFormatsV60.td9 // This file describes the Hexagon V60 instruction classes in TableGen format.
DHexagonInstrFormatsV65.td9 // This file describes the Hexagon V60 instruction classes in TableGen format.
/external/llvm/lib/Target/Hexagon/
DHexagonSubtarget.h42 V4, V5, V55, V60 enumerator
94 bool hasV60TOps() const { return getHexagonArchVersion() >= V60; } in hasV60TOps()
95 bool hasV60TOpsOnly() const { return getHexagonArchVersion() == V60; } in hasV60TOpsOnly()
DHexagonSchedule.td20 // V60 Machine Info -
DHexagonScheduleV60.td61 // There are four SLOTS (four parallel pipelines) in Hexagon V60 machine.
78 // in the CVI co-processor in the Hexagon V60 machine.
310 // Hexagon V60 Resource Definitions -
DHexagonSubtarget.cpp74 { "hexagonv60", V60 }, in initializeSubtargetDependencies()
/external/llvm-project/llvm/test/MC/Hexagon/
Dbug20416.s1 … -triple=hexagon -mv60 -mhvx -filetype=asm %s 2>%t; FileCheck %s --check-prefix=CHECK-V60-ERROR <%t
11 # CHECK-V60-ERROR: rror: invalid instruction packet: slot error
Delf-flags.s3 …nv60 --filetype=obj %s -o - | llvm-readelf --file-headers - | FileCheck --check-prefix=CHECK-V60 %s
8 # CHECK-V60: Flags: 0x60
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonScheduleV60.td10 // There are four SLOTS (four parallel pipelines) in Hexagon V60 machine.
27 // in the CVI co-processor in the Hexagon V60 machine.
79 // Hexagon V60 Resource Definitions -
DHexagonDepArch.td17 …btargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architec…
DHexagonDepArch.h16 enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66 }; enumerator
DHexagonInstrFormatsV60.td9 // This file describes the Hexagon V60 instruction classes in TableGen format.
DHexagonSubtarget.h137 return getHexagonArchVersion() >= Hexagon::ArchEnum::V60; in hasV60Ops()
140 return getHexagonArchVersion() == Hexagon::ArchEnum::V60; in hasV60OpsOnly()
DHexagonInstrFormatsV65.td9 // This file describes the Hexagon V60 instruction classes in TableGen format.
DHexagonSchedule.td69 // V60 Machine Info -
/external/llvm/test/MC/Hexagon/
Delf-flags.s4 … %s -o - | llvm-readobj -file-headers -elf-output-style=GNU | FileCheck --check-prefix=CHECK-V60 %s
9 # CHECK-V60: Flags: 0x60
/external/llvm-project/clang/include/clang/Basic/
DBuiltinsHexagon.def28 #pragma push_macro("V60")
29 #define V60 "v60|" V62
31 #define V55 "v55|" V60
129 #pragma pop_macro("V60")
DBuiltinsHexagonDep.def860 // V60 Scalar Instructions.
862 TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_r, "iiUIi", "", V60)
863 TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_p, "LLiLLiUIi", "", V60)
864 TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_r_acc, "iiiUIi", "", V60)
865 TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_p_acc, "LLiLLiLLiUIi", "", V60)
866 TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_r_nac, "iiiUIi", "", V60)
867 TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_p_nac, "LLiLLiLLiUIi", "", V60)
868 TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_r_xacc, "iiiUIi", "", V60)
869 TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_p_xacc, "LLiLLiLLiUIi", "", V60)
870 TARGET_BUILTIN(__builtin_HEXAGON_S6_rol_i_r_and, "iiiUIi", "", V60)
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dnv_store_vec.ll3 ; Check that we generate new value stores in V60.
Dswp-vsum.ll11 ; V60 does not pipeline due to latencies.
Dpred-taken-jump.ll3 ; Predicated (old) taken jumps weren't supported prior to V60. The purpose

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