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Searched refs:VAL4 (Results 1 – 18 of 18) sorted by relevance

/external/tensorflow/tensorflow/compiler/mlir/xla/tests/
Dlegalize-tf-control-flow.mlir11 // CHECK: [[VAL4:%.+]] = "mhlo.get_tuple_element"([[THEN_ARG]]) {index = 0 : i32}
13 // CHECK: [[VAL6:%.+]] = call @cond_true([[VAL4]], [[VAL5]])
18 // CHECK: [[VAL4:%.+]] = "mhlo.get_tuple_element"([[ELSE_ARG]]) {index = 0 : i32}
20 // CHECK: [[VAL6:%.+]] = call @cond_false([[VAL4]], [[VAL5]])
70 // CHECK: [[VAL4:%.+]] = "mhlo.get_tuple_element"([[VAL3]]) {index = 0 : i32}
71 // CHECK: return [[VAL4]]
129 // CHECK: [[VAL4:%.+]] = "mhlo.get_tuple_element"([[BRANCH0_ARG]]) {index = 0 : i32}
130 // CHECK: [[VAL5:%.+]] = "mhlo.exponential"([[VAL4]])
132 // CHECK: "mhlo.return"([[VAL5]], [[VAL4]])
136 // CHECK: [[VAL4:%.+]] = "mhlo.get_tuple_element"([[BRANCH1_ARG]]) {index = 0 : i32}
[all …]
/external/protobuf/objectivec/Tests/
DGPBDictionaryTests.pddm47 …, KisP, KSUFFIX, KEY1, KEY2, KEY3, KEY4, VALUE_NAME, VALUE_TYPE, VACCESSOR, VAL1, VAL2, VAL3, VAL4)
48 …X, KEY1, KEY2, KEY3, KEY4, VALUE_NAME, VALUE_TYPE, , value, POD, VACCESSOR, VAL1, VAL2, VAL3, VAL4)
50 …T_VALUE(KEY_NAME, KEY_TYPE, KEY1, KEY2, KEY3, KEY4, VALUE_NAME, VALUE_TYPE, VAL1, VAL2, VAL3, VAL4)
51 … KEY1, KEY2, KEY3, KEY4, VALUE_NAME, VALUE_TYPE, Objects, object, OBJECT, , VAL1, VAL2, VAL3, VAL4)
60 …Y2, KEY3, KEY4, VALUE_NAME, VALUE_TYPE, VSUFFIX, VNAME, VHELPER, VACCESSOR, VAL1, VAL2, VAL3, VAL4)
147 //% const VALUE_TYPE k##VNAME$u##s2[] = { VAL1, VAL4, VAL3 };
148 //% const VALUE_TYPE k##VNAME$u##s3[] = { VAL1, VAL2, VAL3, VAL4 };
199 //% const VALUE_TYPE k##VNAME$u##s[] = { VAL1, VAL2, VAL3, VAL4 };
220 //% const VALUE_TYPE k##VNAME$u##s[] = { VAL1, VAL2, VAL3, VAL4 };
247 //% const VALUE_TYPE k##VNAME$u##s[] = { VAL2, VAL3, VAL4 };
[all …]
DGPBArrayTests.m90 //%PDDM-DEFINE ARRAY_TESTS(NAME, TYPE, VAL1, VAL2, VAL3, VAL4)
91 //%ARRAY_TESTS2(NAME, TYPE, VAL1, VAL2, VAL3, VAL4, )
92 //%PDDM-DEFINE ARRAY_TESTS2(NAME, TYPE, VAL1, VAL2, VAL3, VAL4, HELPER)
137 //% static const TYPE kValues[] = { VAL1, VAL2, VAL3, VAL4 };
146 //% XCTAssertEqual([array valueAtIndex:3], VAL4);
192 //% const TYPE kValues2[] = { VAL1, VAL4, VAL3 };
193 //% const TYPE kValues3[] = { VAL1, VAL2, VAL3, VAL4 };
233 //% const TYPE kValues[] = { VAL1, VAL2, VAL3, VAL4 };
250 //% const TYPE kValues[] = { VAL1, VAL2, VAL3, VAL4 };
277 //% const TYPE kValues2[] = { VAL4, VAL1 };
[all …]
/external/elfutils/tests/
Dcleanup-13.c20 #define VAL4(x) ((x)>>24)&0xff,((x)>>16)&0xff,((x)>>8)&0xff,(x)&0xff macro
24 #define VAL4(x) (x)&0xff,((x)>>8)&0xff,((x)>>16)&0xff,((x)>>24)&0xff macro
31 #define OP_const4u(x) 0x0c,VAL4(x),
32 #define OP_const4s(x) 0x0d,VAL4(x),
173 #define OP_call4(x) 0x99,VAL4(x),
/external/tensorflow/tensorflow/compiler/mlir/hlo/tests/
Dlower-complex.mlir72 // CHECK-DAG: [[VAL4:%.+]] = mhlo.multiply %arg1, %arg2
73 // CHECK-DAG: [[VAL5:%.+]] = mhlo.add [[VAL3]], [[VAL4]]
91 // CHECK-DAG: [[VAL4:%.+]] = mhlo.multiply %arg1, %arg2
92 // CHECK-DAG: [[VAL5:%.+]] = mhlo.add [[VAL3]], [[VAL4]]
116 // CHECK-DAG: [[VAL4:%.+]] = mhlo.multiply %arg2, %arg2
118 // CHECK-DAG: [[VAL6:%.+]] = mhlo.add [[VAL4]], [[VAL5]]
155 // CHECK-DAG: [[VAL4:%.+]] = mhlo.multiply %arg2, %arg2
157 // CHECK-DAG: [[VAL6:%.+]] = mhlo.add [[VAL4]], [[VAL5]]
Dlegalize-control-flow.mlir11 //CHECK: [[VAL4:%.+]] = mhlo.add [[VAL3]], [[VAL3]]
12 //CHECK: br ^bb1([[VAL4]] : tensor<i64>)
49 // CHECK: ^bb2([[VAL4:%.+]]: tensor<f32>):
50 // CHECK: [[VAL5:%.+]] = "mhlo.exponential"([[VAL4]]) : (tensor<f32>) -> tensor<f32>
/external/llvm-project/llvm/test/TableGen/
DDag.td66 def VAL4 : bar<foo2, somedef2>;
67 // CHECK: def VAL4 {
/external/llvm/test/TableGen/
DDag.td67 def VAL4 : bar<foo2, somedef2>;
68 // CHECK: def VAL4 {
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dlarge-stack.ll41 ; CHECK-NEXT: mov x[[VAL4:[0-9]+]], #8
42 ; CHECK-NEXT: madd x[[INDEX]], x[[INDEX]], x[[VAL4]], x[[VAL3]]
/external/tensorflow/tensorflow/compiler/mlir/xla/tests/translate/
Dif.mlir58 // CHECK: %[[VAL4:.+]] = f32[] get-tuple-element((f32[]) %[[VAL3]]), index=0
61 // CHECK: ROOT %[[VAL5:.+]] = (f32[]) tuple(f32[] %[[VAL4]])
Dimport.hlotxt688 // CHECK: [[VAL4:%.*]] = "mhlo.reduce"([[VAL3]], [[ARG2]])
693 // CHECK: %4 = mhlo.subtract [[VAL2]], [[VAL4]] : tensor<f32>
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dconstant-fold-imm-immreg.mir60 # GCN: [[VAL4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 63, implicit $exec
61 # GCN: FLAT_STORE_DWORD %10, [[VAL4]],
175 # GCN: [[VAL4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
176 # GCN: FLAT_STORE_DWORD %10, [[VAL4]],
299 # GCN: [[VAL4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
300 # GCN: FLAT_STORE_DWORD %10, [[VAL4]],
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dlower_tf.mlir290 // CHECK-DAG: [[VAL4:%.+]] = "tf.Const"() {value = dense<[2, 0, 1, 3]> : tensor<4xi64>}
294 // CHECK-DAG: [[VAL7:%.+]] = "tf.Transpose"([[VAL6]], [[VAL4]])
340 // CHECK-DAG: [[VAL4:%.+]] = "tf.Const"() {value = dense<[1, 8, 2]> : tensor<3xi64>}
344 // CHECK-DAG: [[VAL8:%.+]] = "tf.Slice"([[VAL7]], [[VAL3]], [[VAL4]])
358 // CHECK-DAG: [[VAL4:%.+]] = "tf.Const"() {value = dense<5.000000e-01> : tensor<f32>}
362 // CHECK-DAG: [[VAL8:%.+]] = "tf.AddV2"([[VAL7]], [[VAL4]])
377 // CHECK-DAG: [[VAL4:%.+]] = "tf.Sub"(%arg2, %arg1)
378 // CHECK-DAG: [[VAL5:%.+]] = "tf.Div"([[VAL4]], [[VAL1]])
379 // CHECK-DAG: [[VAL6:%.+]] = "tf.Div"([[VAL1]], [[VAL4]])
836 // CHECK: [[VAL4:%.+]] = "tf.Reshape"(%arg0, [[VAL2]])
[all …]
/external/conscrypt/benchmark-jmh/
Dbuild.gradle94 // Param strings are in the form "param:VAL1,VAL2;param2:VAL3,VAL4"
/external/llvm-project/mlir/test/Dialect/Linalg/
Dfusion-tensor.mlir381 // CHECK: %[[VAL4:.+]] = subi %[[VAL3]], %[[SUB_OPERAND2]] : i32
382 // CHECK: linalg.yield %[[VAL4]] : i32
/external/llvm-project/mlir/test/IR/
Dparser.mlir1326 // CHECK: [[VAL4:.*]] = "baz"() : () -> i64
1359 // CHECK: [[VAL2:%.*]] = "test.ssacfg_region"([[VAL1]], [[VAL2]], [[VAL3]], [[VAL4:%.*]]) ( {
1360 // CHECK: [[VAL5:%.*]] = "op2"([[VAL1]], [[VAL2]], [[VAL3]], [[VAL4]]) : (i32, i32, i32, i32) -…
1362 // CHECK: [[VAL3]] = "op2"([[VAL1]], [[VAL4]]) : (i32, i32) -> i32
1363 // CHECK: [[VAL4]] = "op3"([[VAL1]]) : (i32) -> i32
/external/tensorflow/tensorflow/compiler/mlir/xla/tests/hlo_to_lhlo_with_xla/
Dops.mlir750 …]]: tensor<f32>, %[[VAL2:.*]]: tensor<i32>, %[[VAL3:.*]]: tensor<f32>, %[[VAL4:.*]]: tensor<i32>):…
752 // CHECK: %[[VAL6:.*]] = mhlo.maximum %[[VAL2]], %[[VAL4:.*]] : tensor<i32>
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Darm64-irtranslator.ll354 ; CHECK: [[VAL4:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, !range !0)
355 ; CHECK: [[SUM4:%[0-9]+]]:_(s64) = G_ADD [[SUM3]], [[VAL4]]