Home
last modified time | relevance | path

Searched refs:VALU (Results 1 – 25 of 63) sorted by relevance

123

/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td18 field bit VALU = 0;
27 // VALU instruction formats.
140 let TSFlags{1} = VALU;
213 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
229 let VALU = 1;
365 let VALU = 1;
DSISchedule.td30 // Normal 16 or 32 bit VALU instructions
36 // Other quarter rate VALU instructions
62 // FIXME: Should there be a class for instructions which are VALU
63 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
DGCNHazardRecognizer.h81 int checkVALUHazards(MachineInstr *VALU);
DVOPInstructions.td40 let VALU = 1;
118 let VALU = 1;
497 let VALU = 1;
617 let VALU = 1;
681 let VALU = 1;
713 let VALU = 1;
DSIDefines.h22 VALU = 1 << 1, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td18 field bit VALU = 0;
27 // VALU instruction formats.
132 let TSFlags{1} = VALU;
207 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
223 let VALU = 1;
359 let VALU = 1;
DGCNHazardRecognizer.h81 int checkVALUHazards(MachineInstr *VALU);
DSISchedule.td54 // FIXME: Should there be a class for instructions which are VALU
55 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
DVOPInstructions.td37 let VALU = 1;
115 let VALU = 1;
491 let VALU = 1;
607 let VALU = 1;
667 let VALU = 1;
699 let VALU = 1;
DSIDefines.h22 VALU = 1 << 1, enumerator
DSIInstrInfo.h342 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
346 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
/external/mesa3d/src/amd/compiler/
DREADME-ISA.md170 A VALU instruction or an `s_waitcnt vmcnt(0)` between the two instructions.
175 An SMEM instruction reads an SGPR. Then, a VALU instruction writes that same SGPR.
210 Mitigated by: any VALU instruction except `v_nop`.
215 Any non-VALU instruction reads the EXEC mask. Then, any VALU instruction writes the EXEC mask.
218 A VALU instruction that writes an SGPR (or has a valid SDST operand), or `s_waitcnt_depctr 0xfffe`.
/external/llvm/test/CodeGen/AMDGPU/
Dsplit-smrd.ll5 ; the VALU, we are also moving its users to the VALU.
Dsgpr-control-flow.ll63 ; VALU for i1 phi.
Duniform-cfg.ll121 ; be selected for the SALU and then later moved to the VALU.
146 ; be selected for the SALU and then later moved to the VALU.
Dvalu-i1.ll7 ; moved using VALU instructions
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dsplit-smrd.ll5 ; the VALU, we are also moving its users to the VALU.
Ddpp_combine.mir5 # bound_ctrl:0 is set, otherwise the result of DPP VALU op can be undefined.
68 # setting bound_ctrl0 on for the combined DPP VALU op to make old undefined
75 # active src lane result - can combine with old = src1 of the VALU op.
76 # The VALU op should have the same masks as DPP mov as they select lanes
78 # Special case: the bound_ctrl for the combined DPP VALU op isn't important
85 # active src lane result - can combine with old = src1 of the VALU op.
86 # The VALU op should have the same masks as DPP mov as they select
98 # for the unary VALU op
142 # range}) or src lane result - can combine with old = src1 of the VALU op
143 # The DPP VALU op should have the same masks (and bctrl) as DPP mov as they
[all …]
Dcarryout-selection.ll115 ; We select to VALU form to avoid unnecessary s_cselect to copy SCC to VCC
300 ; We select to VALU form to avoid unnecessary s_cselect to copy SCC to VCC
Duniform-cfg.ll119 ; be selected for the SALU and then later moved to the VALU.
144 ; be selected for the SALU and then later moved to the VALU.
/external/llvm/lib/Target/AMDGPU/
DSISchedule.td44 // FIXME: Should there be a class for instructions which are VALU
45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
DSIInstrFormats.td23 field bits<1> VALU = 0;
59 let TSFlags{4} = VALU;
121 let VALU = 1;
158 let VALU = 1;
DSIDefines.h20 VALU = 1 << 4, enumerator
DSIInstrInfo.h192 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
196 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinst-select-ctpop.mir158 # SGPR->VGPR ctpop with VALU add
182 # Scalar ctpop with VALU add

123