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/external/libhevc/common/arm/
Dihevc_sao_band_offset_chroma.s179 VAND.U8 D4,D4,D13 @band_table.val[3] = vand_u8(band_table.val[3], au1_cmp)
189 VAND.U8 D3,D3,D14 @band_table.val[2] = vand_u8(band_table.val[2], au1_cmp)
198 VAND.U8 D2,D2,D15 @band_table.val[1] = vand_u8(band_table.val[1], au1_cmp)
206 VAND.U8 D1,D1,D16 @band_table.val[0] = vand_u8(band_table.val[0], au1_cmp)
253 VAND.U8 D12,D12,D17 @band_table.val[3] = vand_u8(band_table.val[3], au1_cmp)
263 VAND.U8 D11,D11,D18 @band_table.val[2] = vand_u8(band_table.val[2], au1_cmp)
273 VAND.U8 D10,D10,D19 @band_table.val[1] = vand_u8(band_table.val[1], au1_cmp)
281 VAND.U8 D9,D9,D20 @band_table.val[0] = vand_u8(band_table.val[0], au1_cmp)
Dihevc_sao_band_offset_luma.s163 VAND.U8 D4,D4,D12 @band_table.val[3] = vand_u8(band_table.val[3], au1_cmp)
173 VAND.U8 D3,D3,D11 @band_table.val[2] = vand_u8(band_table.val[2], au1_cmp)
183 VAND.U8 D2,D2,D10 @band_table.val[1] = vand_u8(band_table.val[1], au1_cmp)
190 VAND.U8 D1,D1,D9 @band_table.val[0] = vand_u8(band_table.val[0], au1_cmp)
Dihevc_sao_edge_offset_class0_chroma.s221 VAND Q7,Q7,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
240 VAND Q12,Q12,Q4 @II edge_idx = vandq_s8(edge_idx, au1_mask)
386 VAND Q7,Q7,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
406 VAND Q14,Q14,Q4 @II edge_idx = vandq_s8(edge_idx, au1_mask)
Dihevc_sao_edge_offset_class0.s219 VAND Q7,Q7,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
233 VAND Q14,Q14,Q4 @II edge_idx = vandq_s8(edge_idx, au1_mask)
325 VAND Q12,Q12,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
Dihevc_sao_edge_offset_class3.s330 VAND Q9,Q9,Q4 @I edge_idx = vandq_s8(edge_idx, au1_mask)
426 VAND Q13,Q13,Q4 @II edge_idx = vandq_s8(edge_idx, au1_mask)
445 VAND Q9,Q9,Q4 @III edge_idx = vandq_s8(edge_idx, au1_mask)
525 VAND Q13,Q13,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
666 VAND Q13,Q13,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
808 VAND Q13,Q13,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
Dihevc_sao_edge_offset_class2.s312 VAND Q9,Q9,Q4 @I edge_idx = vandq_s8(edge_idx, au1_mask)
398 VAND Q11,Q11,Q4 @II edge_idx = vandq_s8(edge_idx, au1_mask)
413 VAND Q9,Q9,Q4 @III edge_idx = vandq_s8(edge_idx, au1_mask)
488 VAND Q9,Q9,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
625 VAND Q13,Q13,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
756 VAND Q13,Q13,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
Dihevc_sao_edge_offset_class3_chroma.s418 VAND Q9,Q9,Q4 @I edge_idx = vandq_s8(edge_idx, au1_mask)
530 VAND Q13,Q13,Q4 @II edge_idx = vandq_s8(edge_idx, au1_mask)
555 VAND Q9,Q9,Q4 @III edge_idx = vandq_s8(edge_idx, au1_mask)
648 VAND Q9,Q9,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
825 VAND Q13,Q13,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
1001 VAND Q13,Q13,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
Dihevc_sao_edge_offset_class2_chroma.s427 VAND Q11,Q9,Q4 @I edge_idx = vandq_s8(edge_idx, au1_mask)
528 VAND Q13,Q13,Q4 @II edge_idx = vandq_s8(edge_idx, au1_mask)
563 VAND Q9,Q9,Q4 @III edge_idx = vandq_s8(edge_idx, au1_mask)
648 VAND Q13,Q13,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
799 VAND Q13,Q13,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
949 VAND Q13,Q13,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
/external/llvm-project/llvm/test/CodeGen/VE/VELIntrinsics/
Dvand.ll6 ;;; We test VAND*vvl, VAND*vvl_v, VAND*rvl, VAND*rvl_v, VAND*vvml_v,
7 ;;; VAND*rvml_v, PVAND*vvl, PVAND*vvl_v, PVAND*rvl, PVAND*rvl_v, PVAND*vvml_v, and
/external/llvm-project/llvm/test/MC/ARM/
Ddirective-fpu-instrs.s4 VAND d3, d5, d5 define
/external/llvm/test/MC/ARM/
Ddirective-fpu-instrs.s4 VAND d3, d5, d5 define
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dstore-global.ll81 ; GCN: v_mov_b32_e32 [[VAND:v[0-9]+]], [[AND]]
82 ; SIVI: buffer_store_dword [[VAND]]
83 ; GFX9: global_store_dword v{{[0-9]+}}, [[VAND]], s
Dstore-private.ll115 ; SI: v_mov_b32_e32 [[VAND:v[0-9]+]], [[AND]]
116 ; SI: buffer_store_dword [[VAND]]
/external/libopus/celt/arm/
Dcelt_pitch_xcorr_arm_gnu.s84 @ Unlike VMOV, VAND is a data processsing instruction (and doesn't get
112 VAND d4, d5, d5 define
129 @ Use VAND since it's a data processing instruction again.
Dcelt_pitch_xcorr_arm.s81 ; Unlike VMOV, VAND is a data processsing instruction (and doesn't get
109 VAND d4, d5, d5 define
126 ; Use VAND since it's a data processing instruction again.
/external/llvm/test/CodeGen/AMDGPU/
Dstore.ll92 ; SI: v_mov_b32_e32 [[VAND:v[0-9]+]], [[AND]]
93 ; SI: buffer_store_dword [[VAND]]
/external/arm-neon-tests/
Dref-rvct-neon-nofp16.txt4189 VAND/VANDQ output:
4190 VAND/VANDQ:0:result_int8x8 [] = { 0, 0, 2, 2, 0, 0, 2, 2, }
4191 VAND/VANDQ:1:result_int16x4 [] = { fffffff0, fffffff0, fffffff0, fffffff0, }
4192 VAND/VANDQ:2:result_int32x2 [] = { 0, 1, }
4193 VAND/VANDQ:3:result_int64x1 [] = { 60, }
4194 VAND/VANDQ:4:result_uint8x8 [] = { 10, 10, 10, 10, 14, 14, 14, 14, }
4195 VAND/VANDQ:5:result_uint16x4 [] = { 10, 10, 12, 12, }
4196 VAND/VANDQ:6:result_uint32x2 [] = { 20, 20, }
4197 VAND/VANDQ:7:result_uint64x1 [] = { 0, }
4198 VAND/VANDQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
Dref-rvct-neon.txt4719 VAND/VANDQ output:
4720 VAND/VANDQ:0:result_int8x8 [] = { 0, 0, 2, 2, 0, 0, 2, 2, }
4721 VAND/VANDQ:1:result_int16x4 [] = { fffffff0, fffffff0, fffffff0, fffffff0, }
4722 VAND/VANDQ:2:result_int32x2 [] = { 0, 1, }
4723 VAND/VANDQ:3:result_int64x1 [] = { 60, }
4724 VAND/VANDQ:4:result_uint8x8 [] = { 10, 10, 10, 10, 14, 14, 14, 14, }
4725 VAND/VANDQ:5:result_uint16x4 [] = { 10, 10, 12, 12, }
4726 VAND/VANDQ:6:result_uint32x2 [] = { 20, 20, }
4727 VAND/VANDQ:7:result_uint64x1 [] = { 0, }
4728 VAND/VANDQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
Dref-rvct-all.txt4719 VAND/VANDQ output:
4720 VAND/VANDQ:0:result_int8x8 [] = { 0, 0, 2, 2, 0, 0, 2, 2, }
4721 VAND/VANDQ:1:result_int16x4 [] = { fffffff0, fffffff0, fffffff0, fffffff0, }
4722 VAND/VANDQ:2:result_int32x2 [] = { 0, 1, }
4723 VAND/VANDQ:3:result_int64x1 [] = { 60, }
4724 VAND/VANDQ:4:result_uint8x8 [] = { 10, 10, 10, 10, 14, 14, 14, 14, }
4725 VAND/VANDQ:5:result_uint16x4 [] = { 10, 10, 12, 12, }
4726 VAND/VANDQ:6:result_uint32x2 [] = { 20, 20, }
4727 VAND/VANDQ:7:result_uint64x1 [] = { 0, }
4728 VAND/VANDQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleR52.td784 def : InstRW<[R52WriteFPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)d")>;
785 def : InstRW<[R52Write2FPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)q")>;
DARMScheduleSwift.td560 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
/external/llvm-project/llvm/lib/Target/ARM/
DARMScheduleR52.td784 def : InstRW<[R52WriteFPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)d")>;
785 def : InstRW<[R52Write2FPALU_F3, R52Read_F2, R52Read_F2], (instregex "(VAND|VBIC|VEOR)q")>;
DARMScheduleSwift.td560 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
/external/llvm-project/llvm/lib/Target/VE/
DVEInstrVec.td539 // e.g. VAND, VOR, VXOR, and etc.
954 // Section 8.11.1 - VAND (Vector And)
955 let cx = 0, cx2 = 0 in defm VAND : RVLm<"vand", 0xc4, I64, V64, VM>;
/external/llvm/lib/Target/ARM/
DARMScheduleSwift.td544 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",

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