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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dspill-wide-sgpr.ll1 …ch=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VGPR %s
6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
8 ; VGPR: s_cbranch_scc1
10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
33 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
34 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
35 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
36 ; VGPR: s_cbranch_scc1
[all …]
Dfold-fi-operand-shrink.mir6 # First operand is FI is in a VGPR, other operand is a VGPR
30 # First operand is a VGPR, other operand FI is in a VGPR
54 # First operand is FI is in an SGPR, other operand is a VGPR
78 # First operand is an SGPR, other operand FI is in a VGPR
102 # First operand is FI is in an SGPR, other operand is a VGPR
126 # First operand is a VGPR, other operand FI is in an SGPR
150 # First operand is FI is in a VGPR, other operand is an inline imm in a VGPR
171 # First operand is an inline imm in a VGPR, other operand FI is in a VGPR
192 # First operand is FI is in a VGPR, other operand is an literal constant in a VGPR
213 # First operand is a literal constant in a VGPR, other operand FI is in a VGPR
Dcontrol-flow-fastregalloc.ll2 …=1 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VGPR -check-prefix=GCN %s
8 ; FIXME: This checks with SGPR to VGPR spilling disabled, but this may
13 ; VGPR: workitem_private_segment_byte_size = 12{{$}}
26 ; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
27 ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
52 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
53 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
85 ; VGPR: workitem_private_segment_byte_size = 16{{$}}
98 ; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
99 ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
[all …]
Dillegal-sgpr-to-vgpr-copy.ll4 … error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_i32 void (): illegal SGPR to VGPR copy
13 …rror: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v2i32 void (): illegal SGPR to VGPR copy
21 …rror: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v4i32 void (): illegal SGPR to VGPR copy
29 …rror: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v8i32 void (): illegal SGPR to VGPR copy
37 …ror: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v16i32 void (): illegal SGPR to VGPR copy
45 … error: <unknown>:0:0: in function illegal_agpr_to_sgpr_copy_i32 void (): illegal SGPR to VGPR copy
54 …rror: <unknown>:0:0: in function illegal_agpr_to_sgpr_copy_v2i32 void (): illegal SGPR to VGPR copy
Dlo16-hi16-illegal-copy.mir10 … error: <unknown>:0:0: in function lo_to_lo_illegal_vgpr_to_sgpr void (): illegal SGPR to VGPR copy
35 … error: <unknown>:0:0: in function lo_to_lo_illegal_agpr_to_sgpr void (): illegal SGPR to VGPR copy
Dspill-scavenge-offset.ll10 ; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
34 ; mark most VGPR registers as used to increase register pressure
69 ; load VGPR data
95 ; mark most VGPR registers as used to increase register pressure
Dcallee-frame-setup.ll130 ; There is stack usage only because of the need to evict a VGPR for
260 ; Use a copy to a free SGPR instead of introducing a second CSR VGPR.
297 ; Use a copy to a free SGPR instead of introducing a second CSR VGPR.
386 ; Use all clobberable registers, so FP has to spill to a VGPR.
396 ; Need a new CSR VGPR to satisfy the FP spill.
431 ; Use all clobberable registers, so FP has to spill to a VGPR.
448 ; register is needed to access the CSR VGPR slot.
486 ; Use all clobberable registers, so FP has to spill to a VGPR.
493 ; Use all clobberable VGPRs, so a CSR spill is needed for the VGPR
562 ; If we have a reserved VGPR that can be used for SGPR spills, we may still
[all …]
Duse-sgpr-multiple-times.ll138 ; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]]
140 ; GCN: v_fma_f32 [[RESULT0:v[0-9]+]], [[SK]], [[SK]], [[VGPR]]
168 ; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]]
170 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR]], [[SK]], [[SK]]
198 ; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]]
200 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR]], [[SK]], [[SK]]
/external/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td191 [llvm_v4f32_ty], // vdata(VGPR)
192 [llvm_anyint_ty, // vaddr(VGPR)
206 [llvm_v4f32_ty, // vdata(VGPR)
207 llvm_anyint_ty, // vaddr(VGPR)
221 [llvm_i32_ty, // vdata(VGPR)
222 llvm_anyint_ty, // vaddr(VGPR)
243 [llvm_i32_ty, // src(VGPR)
244 llvm_i32_ty, // cmp(VGPR)
245 llvm_anyint_ty, // vaddr(VGPR)
255 llvm_i32_ty, // vindex(VGPR)
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallingConv.td153 (sequence "VGPR%u", 24, 255)
157 (sequence "VGPR%u", 32, 255)
162 (add (sequence "VGPR%u", 40, 47),
163 (sequence "VGPR%u", 56, 63),
164 (sequence "VGPR%u", 72, 79),
165 (sequence "VGPR%u", 88, 95),
166 (sequence "VGPR%u", 104, 111),
167 (sequence "VGPR%u", 120, 127),
168 (sequence "VGPR%u", 136, 143),
169 (sequence "VGPR%u", 152, 159),
[all …]
DSIRegisterInfo.td135 // of the result or reading just 16 bits of a 32 bit VGPR.
137 // Non-VGPR register classes use it as we need to have matching subregisters
282 // VGPR registers
284 defm VGPR#Index :
335 // Give all SGPR classes higher priority than VGPR classes, because
474 (add (sequence "VGPR%u_LO16", 0, 255))> {
481 (add (sequence "VGPR%u_HI16", 0, 255))> {
487 // VGPR 32-bit registers
490 (add (sequence "VGPR%u", 0, 255))> {
496 // VGPR 64-bit registers
[all …]
DSIMachineFunctionInfo.h443 Register VGPR;
447 SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
450 bool hasReg() { return VGPR != 0;}
455 Register VGPR;
461 SGPRSpillVGPRCSR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
518 SpillVGPRs[Index].VGPR = NewVGPR;
DSIFrameLowering.cpp98 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane in getVGPRSpillLaneOrTempRegister()
119 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane << '\n';); in getVGPRSpillLaneOrTempRegister()
930 buildPrologSpill(ST, LiveRegs, MBB, MBBI, TII, Reg.VGPR, in emitPrologue()
991 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill[0].VGPR) in emitPrologue()
994 .addReg(Spill[0].VGPR, RegState::Undef); in emitPrologue()
1009 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill[0].VGPR) in emitPrologue()
1012 .addReg(Spill[0].VGPR, RegState::Undef); in emitPrologue()
1161 .addReg(Spill[0].VGPR) in emitEpilogue()
1186 .addReg(Spill[0].VGPR) in emitEpilogue()
1199 buildEpilogReload(ST, LiveRegs, MBB, MBBI, TII, Reg.VGPR, in emitEpilogue()
[all …]
/external/llvm-project/llvm/docs/AMDGPU/
Dgfx10_addr_mimg.rst15 …and may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA…
19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
20 * If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1, 2, 3, 4, 8 or 16 d…
/external/llvm/lib/Target/AMDGPU/
DSIIntrinsics.td25 llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
27 llvm_i32_ty, // vaddr(VGPR)
41 [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
43 llvm_anyint_ty, // vaddr(VGPR)
57 [llvm_v4f32_ty], // vdata(VGPR)
58 [llvm_anyint_ty, // vaddr(VGPR)
73 [llvm_v4f32_ty], // vdata(VGPR)
74 [llvm_anyint_ty, // vaddr(VGPR)
DSIRegisterInfo.td107 // VGPR registers
109 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
192 // VGPR 32-bit registers
194 (add (sequence "VGPR%u", 0, 255))> {
198 // VGPR 64-bit registers
203 // VGPR 96-bit registers
209 // VGPR 128-bit registers
216 // VGPR 256-bit registers
227 // VGPR 512-bit registers
378 // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
[all …]
DSIMachineFunctionInfo.h124 unsigned VGPR; member
126 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { } in SpilledReg()
127 SpilledReg() : VGPR(AMDGPU::NoRegister), Lane(-1) { } in SpilledReg()
129 bool hasReg() { return VGPR != AMDGPU::NoRegister;} in hasReg()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td437 // The pointer argument is assumed to be dynamically uniform if a VGPR.
690 P_.RetTypes, // vdata(VGPR) -- for load/atomic-with-return
692 !foreach(arg, P_.DataArgs, arg.Type), // vdata(VGPR) -- for store/atomic
694 P_.AddrTypes, // vaddr(VGPR)
860 llvm_i32_ty, // vindex(VGPR)
861 llvm_i32_ty, // offset(SGPR/VGPR/imm)
879 [data_ty, // vdata(VGPR)
881 llvm_i32_ty, // vindex(VGPR)
882 llvm_i32_ty, // offset(SGPR/VGPR/imm)
900 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
[all …]
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td454 // The pointer argument is assumed to be dynamically uniform if a VGPR.
717 P_.RetTypes, // vdata(VGPR) -- for load/atomic-with-return
719 !foreach(arg, P_.DataArgs, arg.Type), // vdata(VGPR) -- for store/atomic
721 P_.AddrTypes, // vaddr(VGPR)
896 llvm_i32_ty, // vindex(VGPR)
897 llvm_i32_ty, // offset(SGPR/VGPR/imm)
916 [data_ty, // vdata(VGPR)
918 llvm_i32_ty, // vindex(VGPR)
919 llvm_i32_ty, // offset(SGPR/VGPR/imm)
938 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
[all …]
/external/clang/test/SemaOpenCL/
Damdgpu-num-register-attrs.cl20 // Check 0 VGPR is accepted.
26 // Check both 0 SGPR and VGPR is accepted.
29 // Too large VGPR value.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td199 // VGPR registers
201 def VGPR#Index : SIReg <"v"#Index, Index> {
232 // Give all SGPR classes higher priority than VGPR classes, because
361 // VGPR 32-bit registers
364 (add (sequence "VGPR%u", 0, 255))> {
369 // VGPR 64-bit registers
372 // VGPR 96-bit registers
375 // VGPR 128-bit registers
378 // VGPR 160-bit registers
381 // VGPR 256-bit registers
[all …]
DSIMachineFunctionInfo.h432 unsigned VGPR = 0;
436 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {}
439 bool hasReg() { return VGPR != 0;}
444 unsigned VGPR;
450 SGPRSpillVGPRCSR(unsigned V, Optional<int> F) : VGPR(V), FI(F) {}
DAMDGPUCallingConv.td85 (sequence "VGPR%u", 24, 255)
89 (sequence "VGPR%u", 32, 255)
98 (sequence "VGPR%u", 0, 255)
/external/llvm/test/CodeGen/AMDGPU/
Dspill-scavenge-offset.ll8 ; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
22 ; mark most VGPR registers as used to increase register pressure
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dregbankselect-amdgcn.s.buffer.load.mir5 # We see the offset is a VGPR, but this is due to a constant for some
6 # reason ending up in a VGPR. This shouldn't really ever happen, but

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