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Searched refs:VIA_MAX_CACHELINE_SIZE (Results 1 – 3 of 3) sorted by relevance

/external/kernel-headers/original/uapi/drm/
Dvia_drm.h44 #define VIA_MAX_CACHELINE_SIZE 64 macro
47 (VIA_MAX_CACHELINE_SIZE - 1)) & \
48 ~(VIA_MAX_CACHELINE_SIZE - 1)) + \
49 VIA_MAX_CACHELINE_SIZE*(lockNo)))
200 char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
/external/libdrm/include/drm/
Dvia_drm.h45 #define VIA_MAX_CACHELINE_SIZE 64 macro
48 (VIA_MAX_CACHELINE_SIZE - 1)) & \
49 ~(VIA_MAX_CACHELINE_SIZE - 1)) + \
50 VIA_MAX_CACHELINE_SIZE*(lockNo)))
201 char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
/external/igt-gpu-tools/include/drm-uapi/
Dvia_drm.h44 #define VIA_MAX_CACHELINE_SIZE 64 macro
47 (VIA_MAX_CACHELINE_SIZE - 1)) & \
48 ~(VIA_MAX_CACHELINE_SIZE - 1)) + \
49 VIA_MAX_CACHELINE_SIZE*(lockNo)))
200 char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];