| /external/flatbuffers/swift/Sources/FlatBuffers/ |
| D | FlatBufferBuilder.swift | 97 let isOkay = _bb.read(def: VOffset.self, position: startTable + Int(field)) != 0 in require()
150 let sizeofVoffset = MemoryLayout<VOffset>.size in endTable()
166 _bb.push(value: VOffset(off), len: sizeofVoffset) in endTable()
169 _bb.push(value: VOffset(tableObjectSize), len: sizeofVoffset) in endTable()
255 fileprivate func track(offset: UOffset, at position: VOffset) { in track()
423 public func add<T>(offset: Offset<T>, at position: VOffset) { in add<T>()
447 public func add<T: Scalar>(element: T, def: T, at position: VOffset) { in add<T: Scalar>()
461 public func add(condition: Bool, def: Bool, at position: VOffset) { in add()
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| D | Constants.swift | 15 public typealias VOffset = UInt16 typealias
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| D | Table.swift | 17 …return o < bb.read(def: VOffset.self, position: Int(vtable)) ? Int32(bb.read(def: Int16.self, posi… in offset()
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| /external/flatbuffers/tests/FlatBuffers.Test.Swift/Tests/FlatBuffers.Test.SwiftTests/ |
| D | FlatbuffersDoubleTests.swift | 34 static let offsets: (name: VOffset, lan: VOffset, lng: VOffset) = (4,6,8)
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| D | FlatBuffersTests.swift | 73 static let offsets: (name: VOffset, lan: VOffset, lng: VOffset) = (0, 1, 2)
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| D | FlatBuffersStructsTests.swift | 116 private let VPointerVectorVecOffsets: (color: VOffset, vector: VOffset) = (0, 1)
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| D | FlatBuffersUnionTests.swift | 198 static let offsets: (name: VOffset, dmg: VOffset) = (0, 1)
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCodeEmitter.cpp | 141 unsigned VOffset = 0; in EncodeSingleInstruction() local
155 ++VOffset; in EncodeSingleInstruction()
179 HexagonMCInstrInfo::isVector(MCII, HMB) ? VOffset : SOffset; in EncodeSingleInstruction()
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| /external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCodeEmitter.cpp | 730 unsigned VOffset = 0; in getMachineOpValue() local
749 ++VOffset; in getMachineOpValue()
771 unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset in getMachineOpValue()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCodeEmitter.cpp | 736 unsigned VOffset = 0; in getMachineOpValue() local
753 ++VOffset; in getMachineOpValue()
775 unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset in getMachineOpValue()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 3639 Register VOffset = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferStore() local
3650 std::tie(VOffset, ImmOffset, TotalOffset) = splitBufferOffsets(B, VOffset); in legalizeBufferStore()
3682 .addUse(VOffset) // voffset in legalizeBufferStore()
3722 Register VOffset = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferLoad() local
3740 std::tie(VOffset, ImmOffset, TotalOffset) = splitBufferOffsets(B, VOffset); in legalizeBufferLoad()
3785 .addUse(VOffset) // voffset in legalizeBufferLoad()
3916 Register VOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferAtomic() local
3924 std::tie(VOffset, ImmOffset, TotalOffset) = splitBufferOffsets(B, VOffset); in legalizeBufferAtomic()
3943 .addUse(VOffset) // voffset in legalizeBufferAtomic()
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| D | AMDGPUInstructionSelector.cpp | 2923 MachineOperand &VOffset = MI.getOperand(4); in selectAMDGPU_BUFFER_ATOMIC_FADD() local
2927 bool HasVOffset = !isOperandImmEqual(VOffset, 0, *MRI); in selectAMDGPU_BUFFER_ATOMIC_FADD()
2965 .addReg(VOffset.getReg()) in selectAMDGPU_BUFFER_ATOMIC_FADD()
2972 I.add(VOffset); in selectAMDGPU_BUFFER_ATOMIC_FADD()
3554 Register VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectGlobalSAddr() local
3557 VOffset) in selectGlobalSAddr()
3562 [=](MachineInstrBuilder &MIB) { MIB.addReg(VOffset); }, // voffset in selectGlobalSAddr()
3577 Register VOffset = matchZeroExtendFromS32(*MRI, PtrBaseOffset); in selectGlobalSAddr() local
3578 if (!VOffset) in selectGlobalSAddr()
3585 MIB.addReg(VOffset); in selectGlobalSAddr()
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| D | AMDGPUISelDAGToDAG.cpp | 246 SDValue &VOffset, SDValue &Offset) const;
1818 SDValue &VOffset, in SelectGlobalSAddr() argument
1845 VOffset = SDValue(VMov, 0); in SelectGlobalSAddr()
1865 VOffset = SDValue(VMov, 0); in SelectGlobalSAddr()
1877 VOffset = ZextRHS; in SelectGlobalSAddr()
1885 VOffset = ZextLHS; in SelectGlobalSAddr()
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| D | AMDGPURegisterBankInfo.cpp | 1445 Register VOffset; in applyMappingSBufferLoad() local
1449 VOffset, SOffset, ImmOffset, Alignment); in applyMappingSBufferLoad()
1491 .addUse(VOffset) // voffset in applyMappingSBufferLoad()
1801 Register VOffset = MI.getOperand(3).getReg(); in selectStoreIntrinsic() local
1806 std::tie(VOffset, ImmOffset) = splitBufferOffsets(B, VOffset); in selectStoreIntrinsic()
1808 const bool Offen = !isZero(VOffset, MRI); in selectStoreIntrinsic()
1837 MIB.addUse(VOffset); in selectStoreIntrinsic()
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| D | SIISelLowering.cpp | 6752 static unsigned getBufferOffsetForMMO(SDValue VOffset, in getBufferOffsetForMMO() argument
6757 if (!isa<ConstantSDNode>(VOffset) || !isa<ConstantSDNode>(SOffset) || in getBufferOffsetForMMO()
6766 return cast<ConstantSDNode>(VOffset)->getSExtValue() + in getBufferOffsetForMMO()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 117 SDValue &ImmOffset, SDValue &VOffset) const;
1038 SDValue &VOffset) const { in SelectMUBUFIntrinsicVOffset()
1057 VOffset = N0; in SelectMUBUFIntrinsicVOffset()
1064 VOffset = Offset; in SelectMUBUFIntrinsicVOffset()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 987 Register VOffset = MI.getOperand(3).getReg(); in selectStoreIntrinsic() local
993 std::tie(VOffset, ImmOffset, TotalOffset) = splitBufferOffsets(B, VOffset); in selectStoreIntrinsic()
997 const bool Offen = !isZero(VOffset, *MRI); in selectStoreIntrinsic()
1008 MIB.addUse(VOffset); in selectStoreIntrinsic()
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| D | AMDGPURegisterBankInfo.cpp | 1380 Register VOffset = MI.getOperand(3).getReg(); in selectStoreIntrinsic() local
1385 std::tie(VOffset, ImmOffset) = splitBufferOffsets(B, VOffset); in selectStoreIntrinsic()
1387 const bool Offen = !isZero(VOffset, MRI); in selectStoreIntrinsic()
1416 MIB.addUse(VOffset); in selectStoreIntrinsic()
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| D | SIISelLowering.cpp | 6115 static unsigned getBufferOffsetForMMO(SDValue VOffset, in getBufferOffsetForMMO() argument
6120 if (!isa<ConstantSDNode>(VOffset) || !isa<ConstantSDNode>(SOffset) || in getBufferOffsetForMMO()
6129 return cast<ConstantSDNode>(VOffset)->getSExtValue() + in getBufferOffsetForMMO()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 25947 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4; in combineTargetShuffle() local
25951 WordMask[i + VOffset] = VMask[i] + VOffset; in combineTargetShuffle()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 34856 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4; in combineTargetShuffle() local
34860 WordMask[i + VOffset] = VMask[i] + VOffset; in combineTargetShuffle()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 37197 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4; in combineTargetShuffle() local
37201 WordMask[i + VOffset] = VMask[i] + VOffset; in combineTargetShuffle()
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