| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 2951 VREV16 output:
2952 VREV16:0:result_int8x8 [] = { fffffff1, fffffff0, fffffff3, fffffff2, fffffff5, fffffff4, fffffff7,…
2953 VREV16:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
2954 VREV16:2:result_int32x2 [] = { 33333333, 33333333, }
2955 VREV16:3:result_int64x1 [] = { 3333333333333333, }
2956 VREV16:4:result_uint8x8 [] = { f1, f0, f3, f2, f5, f4, f7, f6, }
2957 VREV16:5:result_uint16x4 [] = { 3333, 3333, 3333, 3333, }
2958 VREV16:6:result_uint32x2 [] = { 33333333, 33333333, }
2959 VREV16:7:result_uint64x1 [] = { 3333333333333333, }
2960 VREV16:8:result_poly8x8 [] = { f1, f0, f3, f2, f5, f4, f7, f6, }
[all …]
|
| D | ref-rvct-neon.txt | 3371 VREV16 output:
3372 VREV16:0:result_int8x8 [] = { fffffff1, fffffff0, fffffff3, fffffff2, fffffff5, fffffff4, fffffff7,…
3373 VREV16:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
3374 VREV16:2:result_int32x2 [] = { 33333333, 33333333, }
3375 VREV16:3:result_int64x1 [] = { 3333333333333333, }
3376 VREV16:4:result_uint8x8 [] = { f1, f0, f3, f2, f5, f4, f7, f6, }
3377 VREV16:5:result_uint16x4 [] = { 3333, 3333, 3333, 3333, }
3378 VREV16:6:result_uint32x2 [] = { 33333333, 33333333, }
3379 VREV16:7:result_uint64x1 [] = { 3333333333333333, }
3380 VREV16:8:result_poly8x8 [] = { f1, f0, f3, f2, f5, f4, f7, f6, }
[all …]
|
| D | ref-rvct-all.txt | 3371 VREV16 output:
3372 VREV16:0:result_int8x8 [] = { fffffff1, fffffff0, fffffff3, fffffff2, fffffff5, fffffff4, fffffff7,…
3373 VREV16:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
3374 VREV16:2:result_int32x2 [] = { 33333333, 33333333, }
3375 VREV16:3:result_int64x1 [] = { 3333333333333333, }
3376 VREV16:4:result_uint8x8 [] = { f1, f0, f3, f2, f5, f4, f7, f6, }
3377 VREV16:5:result_uint16x4 [] = { 3333, 3333, 3333, 3333, }
3378 VREV16:6:result_uint32x2 [] = { 33333333, 33333333, }
3379 VREV16:7:result_uint64x1 [] = { 3333333333333333, }
3380 VREV16:8:result_poly8x8 [] = { f1, f0, f3, f2, f5, f4, f7, f6, }
[all …]
|
| D | expected_input4gcc-nofp16.txt | 3014 VREV16 output:
|
| D | expected_input4gcc.txt | 3218 VREV16 output:
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 155 VREV16, // reverse elements within 16-bit halfwords enumerator
|
| D | ARMScheduleSwift.td | 549 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
|
| D | ARMISelLowering.cpp | 1210 case ARMISD::VREV16: return "ARMISD::VREV16"; in getTargetNodeName()
4709 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1); in getCTPOP16BitCounts()
6149 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); in GeneratePerfectShuffle()
6273 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); in LowerVECTOR_SHUFFLE()
|
| D | ARMInstrNEON.td | 576 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
6306 // VREV16 : Vector Reverse elements within 16-bit halfwords
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 196 VREV16, // reverse elements within 16-bit halfwords enumerator
|
| D | ARMScheduleSwift.td | 565 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
|
| D | ARMISelLowering.cpp | 1646 case ARMISD::VREV16: return "ARMISD::VREV16"; in getTargetNodeName()
7700 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); in GeneratePerfectShuffle()
8002 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); in LowerVECTOR_SHUFFLE()
|
| D | ARMInstrInfo.td | 259 def ARMvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
|
| D | ARMInstrNEON.td | 6855 // VREV16 : Vector Reverse elements within 16-bit halfwords
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 199 VREV16, // reverse elements within 16-bit halfwords enumerator
|
| D | ARMScheduleSwift.td | 565 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
|
| D | ARMISelLowering.cpp | 1712 case ARMISD::VREV16: return "ARMISD::VREV16"; in getTargetNodeName()
8006 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); in GeneratePerfectShuffle()
8308 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); in LowerVECTOR_SHUFFLE()
9554 unsigned RevOpcode = NumActiveLanes == 16 ? ARMISD::VREV16 : ARMISD::VREV32; in LowerVecReduce()
|
| D | ARMInstrInfo.td | 262 def ARMvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
312 // bitconvert would have to emit a VREV16.8 instruction, whereas the
|
| D | ARMInstrNEON.td | 6906 // VREV16 : Vector Reverse elements within 16-bit halfwords
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 785 def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>;
|
| /external/llvm-project/clang/include/clang/Basic/ |
| D | arm_neon.td | 641 def VREV16 : WOpInst<"vrev16", "..", "cUcPcQcQUcQPc", OP_REV16>;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenFastISel.inc | 418 // FastEmit functions for ARMISD::VREV16.
2751 case ARMISD::VREV16: return fastEmit_ARMISD_VREV16_r(VT, RetVT, Op0, Op0IsKill);
|
| D | ARMGenDAGISel.inc | 63854 /*140882*/ /*SwitchOpcode*/ 69, TARGET_VAL(ARMISD::VREV16),// ->140954
|