| /external/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| D | PPCCallLowering.cpp | 27 const Value *Val, ArrayRef<Register> VRegs, in lowerReturn() argument
29 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && in lowerReturn()
31 if (VRegs.size() > 0) in lowerReturn()
40 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments()
45 return VRegs.empty(); in lowerFormalArguments()
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| D | PPCCallLowering.h | 30 ArrayRef<Register> VRegs,
33 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | SwiftErrorValueTracking.cpp | 181 SmallVector<std::pair<MachineBasicBlock *, Register>, 4> VRegs; in propagateVRegs() local
186 VRegs.push_back(std::make_pair( in propagateVRegs()
204 VRegs.size() >= 1 && in propagateVRegs()
206 VRegs.begin(), VRegs.end(), in propagateVRegs()
208 -> bool { return V.second != VRegs[0].second; }) != in propagateVRegs()
209 VRegs.end(); in propagateVRegs()
214 assert(!VRegs.empty() && in propagateVRegs()
217 setCurrentVReg(MBB, SwiftErrorVal, VRegs[0].second); in propagateVRegs()
229 assert(!VRegs.empty() && in propagateVRegs()
234 .addReg(VRegs[0].second); in propagateVRegs()
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| D | MIRVRegNamerUtils.cpp | 30 VRegRenamer::getVRegRenameMap(const std::vector<NamedVReg> &VRegs) { in getVRegRenameMap() argument
42 for (const auto &VReg : VRegs) { in getVRegRenameMap()
130 std::vector<NamedVReg> VRegs; in renameInstsInMBB() local
143 VRegs.push_back( in renameInstsInMBB()
147 return VRegs.size() ? doVRegRenaming(getVRegRenameMap(VRegs)) : false; in renameInstsInMBB()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | SwiftErrorValueTracking.cpp | 181 SmallVector<std::pair<MachineBasicBlock *, Register>, 4> VRegs; in propagateVRegs() local
186 VRegs.push_back(std::make_pair( in propagateVRegs()
204 VRegs.size() >= 1 && in propagateVRegs()
206 VRegs.begin(), VRegs.end(), in propagateVRegs()
208 -> bool { return V.second != VRegs[0].second; }) != in propagateVRegs()
209 VRegs.end(); in propagateVRegs()
214 assert(!VRegs.empty() && in propagateVRegs()
217 setCurrentVReg(MBB, SwiftErrorVal, VRegs[0].second); in propagateVRegs()
229 assert(!VRegs.empty() && in propagateVRegs()
234 .addReg(VRegs[0].second); in propagateVRegs()
[all …]
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| D | MIRVRegNamerUtils.cpp | 38 VRegRenamer::getVRegRenameMap(const std::vector<NamedVReg> &VRegs) { in getVRegRenameMap() argument
50 for (const auto &VReg : VRegs) { in getVRegRenameMap()
146 std::vector<NamedVReg> VRegs; in renameInstsInMBB() local
159 VRegs.push_back( in renameInstsInMBB()
163 return VRegs.size() ? doVRegRenaming(getVRegRenameMap(VRegs)) : false; in renameInstsInMBB()
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 39 bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<Register> VRegs, in assignVRegs() argument
43 for (unsigned i = 0; i < VRegs.size(); ++i) in assignVRegs()
44 if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT)) in assignVRegs()
50 SmallVectorImpl<Register> &VRegs) { in setLeastSignificantFirst() argument
52 std::reverse(VRegs.begin(), VRegs.end()); in setLeastSignificantFirst()
57 SmallVector<Register, 4> VRegs; in handle() local
72 VRegs.clear(); in handle()
76 VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT})); in handle()
78 if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Regs[0], in handle()
105 bool handleSplit(SmallVectorImpl<Register> &VRegs,
[all …]
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| D | MipsCallLowering.h | 38 bool assignVRegs(ArrayRef<Register> VRegs, ArrayRef<CCValAssign> ArgLocs,
41 void setLeastSignificantFirst(SmallVectorImpl<Register> &VRegs);
58 virtual bool handleSplit(SmallVectorImpl<Register> &VRegs,
67 ArrayRef<Register> VRegs) const override;
70 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 39 bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<Register> VRegs, in assignVRegs() argument
43 for (unsigned i = 0; i < VRegs.size(); ++i) in assignVRegs()
44 if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i], VT)) in assignVRegs()
50 SmallVectorImpl<Register> &VRegs) { in setLeastSignificantFirst() argument
52 std::reverse(VRegs.begin(), VRegs.end()); in setLeastSignificantFirst()
57 SmallVector<Register, 4> VRegs; in handle() local
72 VRegs.clear(); in handle()
76 VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT})); in handle()
78 if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Regs[0], in handle()
104 bool handleSplit(SmallVectorImpl<Register> &VRegs,
[all …]
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| D | MipsCallLowering.h | 37 bool assignVRegs(ArrayRef<Register> VRegs, ArrayRef<CCValAssign> ArgLocs,
40 void setLeastSignificantFirst(SmallVectorImpl<Register> &VRegs);
57 virtual bool handleSplit(SmallVectorImpl<Register> &VRegs,
66 ArrayRef<Register> VRegs) const override;
69 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.h | 42 ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
48 ArrayRef<Register> VRegs) const override;
51 ArrayRef<ArrayRef<Register>> VRegs) const;
54 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| D | AMDGPUCallLowering.cpp | 262 const Value *Val, ArrayRef<Register> VRegs, in lowerReturnVal() argument
275 ArgInfo OrigRetInfo(VRegs, Val->getType()); in lowerReturnVal()
282 unpackRegsToOrigType(B, Regs, VRegs[VTSplitIdx], LLTy, PartLLT); in lowerReturnVal()
293 ArrayRef<Register> VRegs) const { in lowerReturn()
300 assert(!Val == VRegs.empty() && "Return value without a vreg"); in lowerReturn()
324 if (!lowerReturnVal(B, Val, VRegs, Ret)) in lowerReturn()
438 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArgumentsKernel()
470 ArrayRef<Register> OrigArgRegs = VRegs[i]; in lowerFormalArgumentsKernel()
567 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments()
574 return lowerFormalArgumentsKernel(B, F, VRegs); in lowerFormalArguments()
[all …]
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.h | 44 ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
50 ArrayRef<Register> VRegs) const override;
53 ArrayRef<ArrayRef<Register>> VRegs) const;
56 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.h | 36 ArrayRef<Register> VRegs) const override;
39 ArrayRef<ArrayRef<Register>> VRegs) const override;
46 ArrayRef<Register> VRegs,
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.h | 36 ArrayRef<Register> VRegs) const override;
39 ArrayRef<ArrayRef<Register>> VRegs) const override;
46 ArrayRef<Register> VRegs,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 189 ArrayRef<Register> VRegs) const { in lowerReturn()
190 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && in lowerReturn()
194 if (!VRegs.empty()) { in lowerReturn()
204 assert(VRegs.size() == SplitEVTs.size() && in lowerReturn()
209 ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)}; in lowerReturn()
213 MIRBuilder.buildUnmerge(Regs, VRegs[i]); in lowerReturn()
329 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments()
351 Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1) in lowerFormalArguments()
354 ArgInfo OrigArg(VRegs[Idx], Arg.getType()); in lowerFormalArguments()
358 MIRBuilder.buildMerge(VRegs[Idx][0], Regs); in lowerFormalArguments()
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| D | X86CallLowering.h | 32 ArrayRef<Register> VRegs) const override;
35 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 189 ArrayRef<Register> VRegs) const { in lowerReturn()
190 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) && in lowerReturn()
194 if (!VRegs.empty()) { in lowerReturn()
204 assert(VRegs.size() == SplitEVTs.size() && in lowerReturn()
209 ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)}; in lowerReturn()
213 MIRBuilder.buildUnmerge(Regs, VRegs[i]); in lowerReturn()
327 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments()
348 Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1) in lowerFormalArguments()
351 ArgInfo OrigArg(VRegs[Idx], Arg.getType()); in lowerFormalArguments()
355 MIRBuilder.buildMerge(VRegs[Idx][0], Regs); in lowerFormalArguments()
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| D | X86CallLowering.h | 32 ArrayRef<Register> VRegs) const override;
35 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVCallLowering.h | 31 ArrayRef<Register> VRegs) const override;
34 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| D | RISCVCallLowering.cpp | 26 ArrayRef<Register> VRegs) const { in lowerReturn()
39 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments()
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVCallLowering.h | 31 ArrayRef<Register> VRegs) const override;
34 ArrayRef<ArrayRef<Register>> VRegs) const override;
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| D | RISCVCallLowering.cpp | 26 ArrayRef<Register> VRegs) const { in lowerReturn()
39 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 265 ArrayRef<Register> VRegs, in lowerReturn() argument
269 return lowerReturn(MIRBuilder, Val, VRegs); in lowerReturn()
277 ArrayRef<Register> VRegs) const { in lowerReturn() argument
293 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments() argument
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 304 ArrayRef<Register> VRegs, in lowerReturn() argument
308 return lowerReturn(MIRBuilder, Val, VRegs); in lowerReturn()
316 ArrayRef<Register> VRegs) const { in lowerReturn() argument
334 ArrayRef<ArrayRef<Register>> VRegs) const { in lowerFormalArguments() argument
|