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Searched refs:VSRI (Results 1 – 15 of 15) sorted by relevance

/external/libopus/celt/arm/
Dcelt_pitch_xcorr_arm_gnu.s138 VSRI.64 d5, d4, #32
151 VSRI.64 d4, d5, #16
Dcelt_pitch_xcorr_arm.s135 VSRI.64 d5, d4, #32
148 VSRI.64 d4, d5, #16
/external/llvm/lib/Target/ARM/
DARMISelLowering.h133 VSRI, // ...right enumerator
DARMScheduleSwift.td546 "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
DARMInstrNEON.td538 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
5546 // VSRI : Vector Shift Right and Insert
5547 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
DARMISelLowering.cpp1199 case ARMISD::VSRI: return "ARMISD::VSRI"; in getTargetNodeName()
10672 VShiftOpc = ARMISD::VSRI; in PerformIntrinsicCombine()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h191 VSRI, enumerator
DAArch64ISelLowering.cpp1763 MAKE_CASE(AArch64ISD::VSRI) in getTargetNodeName()
3750 unsigned Opcode = IsShiftRight ? AArch64ISD::VSRI : AArch64ISD::VSLI; in LowerINTRINSIC_WO_CHAIN()
9221 unsigned Inst = IsShiftRight ? AArch64ISD::VSRI : AArch64ISD::VSLI; in tryLowerToSLI()
DAArch64InstrInfo.td482 def AArch64vsri : SDNode<"AArch64ISD::VSRI", SDT_AArch64vshiftinsert>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleA57.td1127 "VSLI(v8i8|v4i16|v2i32|v1i64)", "VSRI(v8i8|v4i16|v2i32|v1i64)")>;
1131 "VSLI(v16i8|v8i16|v4i32|v2i64)", "VSRI(v16i8|v8i16|v4i32|v2i64)")>;
DARMScheduleSwift.td562 "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
DARMInstrNEON.td6014 // VSRI : Vector Shift Right and Insert
6015 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
/external/llvm-project/llvm/lib/Target/ARM/
DARMScheduleA57.td1120 "VSLI(v8i8|v4i16|v2i32|v1i64)", "VSRI(v8i8|v4i16|v2i32|v1i64)")>;
1124 "VSLI(v16i8|v8i16|v4i32|v2i64)", "VSRI(v16i8|v8i16|v4i32|v2i64)")>;
DARMScheduleSwift.td562 "VBSL", "VBSP", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
DARMInstrNEON.td6012 // VSRI : Vector Shift Right and Insert
6013 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;