| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 4867 VTST/VTSTQ (signed input) output:
4868 VTST/VTSTQ:0:result_int8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
4869 VTST/VTSTQ:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
4870 VTST/VTSTQ:2:result_int32x2 [] = { 33333333, 33333333, }
4871 VTST/VTSTQ:3:result_int64x1 [] = { 3333333333333333, }
4872 VTST/VTSTQ:4:result_uint8x8 [] = { 0, ff, ff, ff, ff, ff, ff, ff, }
4873 VTST/VTSTQ:5:result_uint16x4 [] = { 0, ffff, 0, ffff, }
4874 VTST/VTSTQ:6:result_uint32x2 [] = { 0, ffffffff, }
4875 VTST/VTSTQ:7:result_uint64x1 [] = { 3333333333333333, }
4876 VTST/VTSTQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
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| D | ref-rvct-neon.txt | 5687 VTST/VTSTQ (signed input) output:
5688 VTST/VTSTQ:0:result_int8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
5689 VTST/VTSTQ:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
5690 VTST/VTSTQ:2:result_int32x2 [] = { 33333333, 33333333, }
5691 VTST/VTSTQ:3:result_int64x1 [] = { 3333333333333333, }
5692 VTST/VTSTQ:4:result_uint8x8 [] = { 0, ff, ff, ff, ff, ff, ff, ff, }
5693 VTST/VTSTQ:5:result_uint16x4 [] = { 0, ffff, 0, ffff, }
5694 VTST/VTSTQ:6:result_uint32x2 [] = { 0, ffffffff, }
5695 VTST/VTSTQ:7:result_uint64x1 [] = { 3333333333333333, }
5696 VTST/VTSTQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
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| D | ref-rvct-all.txt | 5687 VTST/VTSTQ (signed input) output:
5688 VTST/VTSTQ:0:result_int8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
5689 VTST/VTSTQ:1:result_int16x4 [] = { 3333, 3333, 3333, 3333, }
5690 VTST/VTSTQ:2:result_int32x2 [] = { 33333333, 33333333, }
5691 VTST/VTSTQ:3:result_int64x1 [] = { 3333333333333333, }
5692 VTST/VTSTQ:4:result_uint8x8 [] = { 0, ff, ff, ff, ff, ff, ff, ff, }
5693 VTST/VTSTQ:5:result_uint16x4 [] = { 0, ffff, 0, ffff, }
5694 VTST/VTSTQ:6:result_uint32x2 [] = { 0, ffffffff, }
5695 VTST/VTSTQ:7:result_uint64x1 [] = { 3333333333333333, }
5696 VTST/VTSTQ:8:result_poly8x8 [] = { 33, 33, 33, 33, 33, 33, 33, 33, }
[all …]
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| D | expected_input4gcc-nofp16.txt | 5108 VTST/VTSTQ (signed input) output:
5132 VTST/VTSTQ (unsigned input) output:
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| D | expected_input4gcc.txt | 5496 VTST/VTSTQ (signed input) output:
5522 VTST/VTSTQ (unsigned input) output:
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 106 VTST, // Vector test bits. enumerator
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| D | ARMScheduleSwift.td | 544 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
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| D | ARMScheduleA9.td | 2408 // VHADD/VRHADD/VQADD/VTST/VADH/VRADH
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| D | ARMInstrNEON.td | 505 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
4797 // VTST : Vector Test Bits
4798 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
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| D | ARMISelLowering.cpp | 1181 case ARMISD::VTST: return "ARMISD::VTST"; in getTargetNodeName()
4958 Opc = ARMISD::VTST; in LowerVSETCC()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 139 VTST, // Vector test bits. enumerator
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| D | ARMScheduleSwift.td | 560 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
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| D | ARMScheduleA57.td | 1011 (instregex "VCEQ", "VCGE", "VCGT", "VCLE", "VTST", "VCLT")>;
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| D | ARMScheduleA9.td | 2431 // VHADD/VRHADD/VQADD/VTST/VADH/VRADH
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| D | ARMInstrNEON.td | 482 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVTST>;
5176 // VTST : Vector Test Bits
5177 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
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| D | ARMISelLowering.cpp | 1615 case ARMISD::VTST: return "ARMISD::VTST"; in getTargetNodeName()
6351 SDValue Result = DAG.getNode(ARMISD::VTST, dl, CmpVT, Op0, Op1); in LowerVSETCC()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 142 VTST, // Vector test bits. enumerator
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| D | ARMScheduleSwift.td | 560 "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
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| D | ARMScheduleA57.td | 1004 (instregex "VCEQ", "VCGE", "VCGT", "VCLE", "VTST", "VCLT")>;
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| D | ARMScheduleA9.td | 2431 // VHADD/VRHADD/VQADD/VTST/VADH/VRADH
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| D | ARMInstrNEON.td | 482 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVTST>;
5169 // VTST : Vector Test Bits
5170 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
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| D | ARMISelLowering.cpp | 1681 case ARMISD::VTST: return "ARMISD::VTST"; in getTargetNodeName()
6544 SDValue Result = DAG.getNode(ARMISD::VTST, dl, CmpVT, Op0, Op1); in LowerVSETCC()
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 566 def VTST : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">;
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| /external/llvm-project/clang/include/clang/Basic/ |
| D | arm_neon.td | 366 def VTST : WInst<"vtst", "U..", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">;
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenFastISel.inc | 3420 // FastEmit functions for ARMISD::VTST.
5487 case ARMISD::VTST: return fastEmit_ARMISD_VTST_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
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