| /external/oboe/samples/RhythmGame/third_party/glm/simd/ |
| D | matrix.h | 300 __m128 Vec0 = _mm_shuffle_ps(Temp0, Temp0, _MM_SHUFFLE(2, 2, 2, 0)); in glm_mat4_determinant_highp() local
340 __m128 Mul03 = _mm_mul_ps(Vec0, Fac0); in glm_mat4_determinant_highp()
352 __m128 Mul06 = _mm_mul_ps(Vec0, Fac1); in glm_mat4_determinant_highp()
364 __m128 Mul09 = _mm_mul_ps(Vec0, Fac2); in glm_mat4_determinant_highp()
640 __m128 Vec0 = _mm_shuffle_ps(Temp0, Temp0, _MM_SHUFFLE(2, 2, 2, 0)); in glm_mat4_inverse() local
680 __m128 Mul03 = _mm_mul_ps(Vec0, Fac0); in glm_mat4_inverse()
692 __m128 Mul06 = _mm_mul_ps(Vec0, Fac1); in glm_mat4_inverse()
704 __m128 Mul09 = _mm_mul_ps(Vec0, Fac2); in glm_mat4_inverse()
861 __m128 Vec0 = _mm_shuffle_ps(Temp0, Temp0, _MM_SHUFFLE(2, 2, 2, 0)); in glm_mat4_inverse_lowp() local
901 __m128 Mul03 = _mm_mul_ps(Vec0, Fac0); in glm_mat4_inverse_lowp()
[all …]
|
| /external/llvm-project/llvm/test/Transforms/PhaseOrdering/X86/ |
| D | vector-reductions.ll | 66 define i32 @TestVectorsEqual(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
96 %arrayidx = getelementptr inbounds i32, i32* %Vec0, i64 %idxprom
128 define i32 @TestVectorsEqual_alt(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
155 %arrayidx = getelementptr inbounds i32, i32* %Vec0, i64 %idxprom
175 define i32 @TestVectorsEqualFP(float* noalias %Vec0, float* noalias %Vec1, float %Tolerance) {
203 %arrayidx = getelementptr inbounds float, float* %Vec0, i64 %idxprom
235 define i32 @TestVectorsEqualFP_alt(float* noalias %Vec0, float* noalias %Vec1, float %Tolerance) {
262 %arrayidx = getelementptr inbounds float, float* %Vec0, i64 %idxprom
|
| /external/oboe/samples/RhythmGame/third_party/glm/detail/ |
| D | func_matrix.inl | 332 tvec4<T, P> Vec0(m[1][0], m[0][0], m[0][0], m[0][0]); local
338 tvec4<T, P> Inv1(Vec0 * Fac0 - Vec2 * Fac3 + Vec3 * Fac4);
339 tvec4<T, P> Inv2(Vec0 * Fac1 - Vec1 * Fac3 + Vec3 * Fac5);
340 tvec4<T, P> Inv3(Vec0 * Fac2 - Vec1 * Fac4 + Vec2 * Fac5);
|
| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | EarlyCSE.cpp | 847 auto *Vec0 = dyn_cast<ConstantVector>(Mask0); in isNonTargetIntrinsicMatch() local
849 if (!Vec0 || !Vec1) in isNonTargetIntrinsicMatch()
851 assert(Vec0->getType() == Vec1->getType() && in isNonTargetIntrinsicMatch()
853 for (int i = 0, e = Vec0->getNumOperands(); i != e; ++i) { in isNonTargetIntrinsicMatch()
854 Constant *Elem0 = Vec0->getOperand(i); in isNonTargetIntrinsicMatch()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAGHVX.cpp | 2087 SDValue Vec0 = N->getOperand(0); in selectShuffle() local
2090 Results.push(TargetOpcode::COPY, ResTy, {Vec0}); in selectShuffle()
2104 Done = scalarizeShuffle(Mask, SDLoc(N), ResTy, Vec0, Vec1, N); in selectShuffle()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAGHVX.cpp | 2048 SDValue Vec0 = N->getOperand(0); in selectShuffle() local
2051 Results.push(TargetOpcode::COPY, ResTy, {Vec0}); in selectShuffle()
2065 Done = scalarizeShuffle(Mask, SDLoc(N), ResTy, Vec0, Vec1, N); in selectShuffle()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 2538 SDValue Vec0 = Op.getOperand(0); in LowerCONCAT_VECTORS() local
2539 EVT VecVT = Vec0.getValueType(); in LowerCONCAT_VECTORS()
2547 return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0); in LowerCONCAT_VECTORS()
2555 SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0); in LowerCONCAT_VECTORS()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrPrefix.td | 1594 dag Vec0 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx0));
1612 Extracts.Vec0>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 4964 SDValue Vec0 = SVN->getOperand(VecIdx0); in lowerVECTOR_SHUFFLE() local
4966 Vec0, DAG.getConstant(EltIdx0, SL, MVT::i32)); in lowerVECTOR_SHUFFLE()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 9794 SDValue Vec0 = Op.getOperand(0); in LowerINSERT_SUBVECTOR() local
9806 SDValue HiVec0 = DAG.getNode(AArch64ISD::UUNPKHI, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
9809 SDValue LoVec0 = DAG.getNode(AArch64ISD::UUNPKLO, DL, WideVT, Vec0); in LowerINSERT_SUBVECTOR()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 5551 SDValue Vec0 = SVN->getOperand(VecIdx0); in lowerVECTOR_SHUFFLE() local
5553 Vec0, DAG.getConstant(EltIdx0, SL, MVT::i32)); in lowerVECTOR_SHUFFLE()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 43311 SDValue Vec0 = N0.getOperand(0); in combineBitOpWithMOVMSK() local
43313 EVT VecVT0 = Vec0.getValueType(); in combineBitOpWithMOVMSK()
43326 DAG.getNode(VecOpc, DL, VecVT0, Vec0, DAG.getBitcast(VecVT0, Vec1)); in combineBitOpWithMOVMSK()
|