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Searched refs:VirtReg2IndexFunctor (Results 1 – 25 of 34) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DVirtRegMap.h51 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysMap;
57 IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
61 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap;
DScheduleDAGInstrs.h79 typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
84 typedef SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMultiMap;
86 typedef SparseMultiSet<VReg2SUnitOperIdx, VirtReg2IndexFunctor>
DFunctionLoweringInfo.h297 IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
DLiveVariables.h120 IndexedMap<VarInfo, VirtReg2IndexFunctor> VirtRegInfo;
DMachineRegisterInfo.h61 VirtReg2IndexFunctor>
71 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
DLiveIntervalAnalysis.h67 IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
DRegisterPressure.h375 SparseSet<unsigned, VirtReg2IndexFunctor> UntiedDefs;
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DVirtRegMap.h52 IndexedMap<Register, VirtReg2IndexFunctor> Virt2PhysMap;
58 IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
62 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap;
DScheduleDAGInstrs.h96 using VReg2SUnitMap = SparseSet<VReg2SUnit, VirtReg2IndexFunctor>;
101 using VReg2SUnitMultiMap = SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor>;
104 SparseMultiSet<VReg2SUnitOperIdx, VirtReg2IndexFunctor>;
DMachineRegisterInfo.h75 VirtReg2IndexFunctor>
80 IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
102 VirtReg2IndexFunctor> RegAllocHints;
138 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
DFunctionLoweringInfo.h286 IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
DLiveVariables.h119 IndexedMap<VarInfo, VirtReg2IndexFunctor> VirtRegInfo;
DLiveIntervals.h68 IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
DRegisterPressure.h393 SparseSet<unsigned, VirtReg2IndexFunctor> UntiedDefs;
DTargetRegisterInfo.h1130 struct VirtReg2IndexFunctor { struct
/external/llvm-project/llvm/include/llvm/CodeGen/
DVirtRegMap.h51 IndexedMap<Register, VirtReg2IndexFunctor> Virt2PhysMap;
57 IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
61 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap;
DScheduleDAGInstrs.h96 using VReg2SUnitMap = SparseSet<VReg2SUnit, VirtReg2IndexFunctor>;
101 using VReg2SUnitMultiMap = SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor>;
104 SparseMultiSet<VReg2SUnitOperIdx, VirtReg2IndexFunctor>;
DMachineRegisterInfo.h75 VirtReg2IndexFunctor>
80 IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
102 VirtReg2IndexFunctor> RegAllocHints;
138 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
DFunctionLoweringInfo.h281 IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
DLiveVariables.h118 IndexedMap<VarInfo, VirtReg2IndexFunctor> VirtRegInfo;
DLiveIntervals.h68 IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
DRegisterPressure.h393 SparseSet<Register, VirtReg2IndexFunctor> UntiedDefs;
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h1085 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { struct
/external/llvm/test/CodeGen/PowerPC/
Dpr15031.ll203 … = type { %"class.std::vector.140", %"struct.std::pair.145", %"struct.llvm::VirtReg2IndexFunctor" }
212 %"struct.llvm::VirtReg2IndexFunctor" = type { i8 }
213 … = type { %"class.std::vector.147", %"struct.std::pair.152", %"struct.llvm::VirtReg2IndexFunctor" }
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dpr15031.ll203 … = type { %"class.std::vector.140", %"struct.std::pair.145", %"struct.llvm::VirtReg2IndexFunctor" }
212 %"struct.llvm::VirtReg2IndexFunctor" = type { i8 }
213 … = type { %"class.std::vector.147", %"struct.std::pair.152", %"struct.llvm::VirtReg2IndexFunctor" }

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