1 /* 2 * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SPM_H 8 #define SPM_H 9 10 /************************************** 11 * Define and Declare 12 **************************************/ 13 14 #define POWERON_CONFIG_EN (SPM_BASE + 0x000) 15 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004) 16 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008) 17 #define SPM_CLK_CON (SPM_BASE + 0x00C) 18 #define SPM_CLK_SETTLE (SPM_BASE + 0x010) 19 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014) 20 #define PCM_CON0 (SPM_BASE + 0x018) 21 #define PCM_CON1 (SPM_BASE + 0x01C) 22 #define PCM_IM_PTR (SPM_BASE + 0x020) 23 #define PCM_IM_LEN (SPM_BASE + 0x024) 24 #define PCM_REG_DATA_INI (SPM_BASE + 0x028) 25 #define PCM_PWR_IO_EN (SPM_BASE + 0x02C) 26 #define PCM_TIMER_VAL (SPM_BASE + 0x030) 27 #define PCM_WDT_VAL (SPM_BASE + 0x034) 28 #define PCM_IM_HOST_RW_PTR (SPM_BASE + 0x038) 29 #define PCM_IM_HOST_RW_DAT (SPM_BASE + 0x03C) 30 #define PCM_EVENT_VECTOR0 (SPM_BASE + 0x040) 31 #define PCM_EVENT_VECTOR1 (SPM_BASE + 0x044) 32 #define PCM_EVENT_VECTOR2 (SPM_BASE + 0x048) 33 #define PCM_EVENT_VECTOR3 (SPM_BASE + 0x04C) 34 #define PCM_EVENT_VECTOR4 (SPM_BASE + 0x050) 35 #define PCM_EVENT_VECTOR5 (SPM_BASE + 0x054) 36 #define PCM_EVENT_VECTOR6 (SPM_BASE + 0x058) 37 #define PCM_EVENT_VECTOR7 (SPM_BASE + 0x05C) 38 #define PCM_EVENT_VECTOR8 (SPM_BASE + 0x060) 39 #define PCM_EVENT_VECTOR9 (SPM_BASE + 0x064) 40 #define PCM_EVENT_VECTOR10 (SPM_BASE + 0x068) 41 #define PCM_EVENT_VECTOR11 (SPM_BASE + 0x06C) 42 #define PCM_EVENT_VECTOR12 (SPM_BASE + 0x070) 43 #define PCM_EVENT_VECTOR13 (SPM_BASE + 0x074) 44 #define PCM_EVENT_VECTOR14 (SPM_BASE + 0x078) 45 #define PCM_EVENT_VECTOR15 (SPM_BASE + 0x07C) 46 #define PCM_EVENT_VECTOR_EN (SPM_BASE + 0x080) 47 #define SPM_SRAM_RSV_CON (SPM_BASE + 0x088) 48 #define SPM_SWINT (SPM_BASE + 0x08C) 49 #define SPM_SWINT_SET (SPM_BASE + 0x090) 50 #define SPM_SWINT_CLR (SPM_BASE + 0x094) 51 #define SPM_SCP_MAILBOX (SPM_BASE + 0x098) 52 #define SCP_SPM_MAILBOX (SPM_BASE + 0x09C) 53 #define SPM_TWAM_CON (SPM_BASE + 0x0A0) 54 #define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4) 55 #define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8) 56 #define SPM_SCP_IRQ (SPM_BASE + 0x0AC) 57 #define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0) 58 #define SPM_IRQ_MASK (SPM_BASE + 0x0B4) 59 #define SPM_SRC_REQ (SPM_BASE + 0x0B8) 60 #define SPM_SRC_MASK (SPM_BASE + 0x0BC) 61 #define SPM_SRC2_MASK (SPM_BASE + 0x0C0) 62 #define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0C4) 63 #define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0C8) 64 #define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x0CC) 65 #define SCP_CLK_CON (SPM_BASE + 0x0D0) 66 #define PCM_DEBUG_CON (SPM_BASE + 0x0D4) 67 #define DDR_EN_DBC_LEN (SPM_BASE + 0x0D8) 68 #define AHB_BUS_CON (SPM_BASE + 0x0DC) 69 #define SPM_SRC3_MASK (SPM_BASE + 0x0E0) 70 #define DDR_EN_EMI_DBC_CON (SPM_BASE + 0x0E4) 71 #define SSPM_CLK_CON (SPM_BASE + 0x0E8) 72 #define PCM_REG0_DATA (SPM_BASE + 0x100) 73 #define PCM_REG1_DATA (SPM_BASE + 0x104) 74 #define PCM_REG2_DATA (SPM_BASE + 0x108) 75 #define PCM_REG3_DATA (SPM_BASE + 0x10C) 76 #define PCM_REG4_DATA (SPM_BASE + 0x110) 77 #define PCM_REG5_DATA (SPM_BASE + 0x114) 78 #define PCM_REG6_DATA (SPM_BASE + 0x118) 79 #define PCM_REG7_DATA (SPM_BASE + 0x11C) 80 #define PCM_REG8_DATA (SPM_BASE + 0x120) 81 #define PCM_REG9_DATA (SPM_BASE + 0x124) 82 #define PCM_REG10_DATA (SPM_BASE + 0x128) 83 #define PCM_REG11_DATA (SPM_BASE + 0x12C) 84 #define PCM_REG12_DATA (SPM_BASE + 0x130) 85 #define PCM_REG13_DATA (SPM_BASE + 0x134) 86 #define PCM_REG14_DATA (SPM_BASE + 0x138) 87 #define PCM_REG15_DATA (SPM_BASE + 0x13C) 88 #define PCM_REG12_MASK_B_STA (SPM_BASE + 0x140) 89 #define PCM_REG12_EXT_DATA (SPM_BASE + 0x144) 90 #define PCM_REG12_EXT_MASK_B_STA (SPM_BASE + 0x148) 91 #define PCM_EVENT_REG_STA (SPM_BASE + 0x14C) 92 #define PCM_TIMER_OUT (SPM_BASE + 0x150) 93 #define PCM_WDT_OUT (SPM_BASE + 0x154) 94 #define SPM_IRQ_STA (SPM_BASE + 0x158) 95 #define SPM_WAKEUP_STA (SPM_BASE + 0x15C) 96 #define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x160) 97 #define SPM_WAKEUP_MISC (SPM_BASE + 0x164) 98 #define BUS_PROTECT_RDY (SPM_BASE + 0x168) 99 #define BUS_PROTECT2_RDY (SPM_BASE + 0x16C) 100 #define SUBSYS_IDLE_STA (SPM_BASE + 0x170) 101 #define CPU_IDLE_STA (SPM_BASE + 0x174) 102 #define PCM_FSM_STA (SPM_BASE + 0x178) 103 #define SRC_REQ_STA (SPM_BASE + 0x17C) 104 #define PWR_STATUS (SPM_BASE + 0x180) 105 #define PWR_STATUS_2ND (SPM_BASE + 0x184) 106 #define CPU_PWR_STATUS (SPM_BASE + 0x188) 107 #define CPU_PWR_STATUS_2ND (SPM_BASE + 0x18C) 108 #define MISC_STA (SPM_BASE + 0x190) 109 #define SPM_SRC_RDY_STA (SPM_BASE + 0x194) 110 #define DRAMC_DBG_LATCH (SPM_BASE + 0x19C) 111 #define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1A0) 112 #define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1A4) 113 #define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1A8) 114 #define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1AC) 115 #define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1B0) 116 #define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1B4) 117 #define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1B8) 118 #define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1BC) 119 #define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1C0) 120 #define SPM_DVFS_STA (SPM_BASE + 0x1C8) 121 #define BUS_PROTECT3_RDY (SPM_BASE + 0x1CC) 122 #define SRC_DDREN_STA (SPM_BASE + 0x1E0) 123 #define MCU_PWR_CON (SPM_BASE + 0x200) 124 #define MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204) 125 #define MP0_CPU0_PWR_CON (SPM_BASE + 0x208) 126 #define MP0_CPU1_PWR_CON (SPM_BASE + 0x20C) 127 #define MP0_CPU2_PWR_CON (SPM_BASE + 0x210) 128 #define MP0_CPU3_PWR_CON (SPM_BASE + 0x214) 129 #define MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218) 130 #define MP1_CPU0_PWR_CON (SPM_BASE + 0x21C) 131 #define MP1_CPU1_PWR_CON (SPM_BASE + 0x220) 132 #define MP1_CPU2_PWR_CON (SPM_BASE + 0x224) 133 #define MP1_CPU3_PWR_CON (SPM_BASE + 0x228) 134 #define MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240) 135 #define MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244) 136 #define MP0_CPU0_L1_PDN (SPM_BASE + 0x248) 137 #define MP0_CPU1_L1_PDN (SPM_BASE + 0x24C) 138 #define MP0_CPU2_L1_PDN (SPM_BASE + 0x250) 139 #define MP0_CPU3_L1_PDN (SPM_BASE + 0x254) 140 #define MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258) 141 #define MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C) 142 #define MP1_CPU0_L1_PDN (SPM_BASE + 0x260) 143 #define MP1_CPU1_L1_PDN (SPM_BASE + 0x264) 144 #define MP1_CPU2_L1_PDN (SPM_BASE + 0x268) 145 #define MP1_CPU3_L1_PDN (SPM_BASE + 0x26C) 146 #define CPU_EXT_BUCK_ISO (SPM_BASE + 0x290) 147 #define DUMMY1_PWR_CON (SPM_BASE + 0x2B0) 148 #define BYPASS_SPMC (SPM_BASE + 0x2B4) 149 #define SPMC_DORMANT_ENABLE (SPM_BASE + 0x2B8) 150 #define ARMPLL_CLK_CON (SPM_BASE + 0x2BC) 151 #define SPMC_IN_RET (SPM_BASE + 0x2C0) 152 #define VDE_PWR_CON (SPM_BASE + 0x300) 153 #define VEN_PWR_CON (SPM_BASE + 0x304) 154 #define ISP_PWR_CON (SPM_BASE + 0x308) 155 #define DIS_PWR_CON (SPM_BASE + 0x30C) 156 #define MFG_CORE1_PWR_CON (SPM_BASE + 0x310) 157 #define AUDIO_PWR_CON (SPM_BASE + 0x314) 158 #define IFR_PWR_CON (SPM_BASE + 0x318) 159 #define DPY_PWR_CON (SPM_BASE + 0x31C) 160 #define MD1_PWR_CON (SPM_BASE + 0x320) 161 #define VPU_TOP_PWR_CON (SPM_BASE + 0x324) 162 #define CONN_PWR_CON (SPM_BASE + 0x32C) 163 #define VPU_CORE2_PWR_CON (SPM_BASE + 0x330) 164 #define MFG_ASYNC_PWR_CON (SPM_BASE + 0x334) 165 #define MFG_PWR_CON (SPM_BASE + 0x338) 166 #define VPU_CORE0_PWR_CON (SPM_BASE + 0x33C) 167 #define VPU_CORE1_PWR_CON (SPM_BASE + 0x340) 168 #define CAM_PWR_CON (SPM_BASE + 0x344) 169 #define MFG_2D_PWR_CON (SPM_BASE + 0x348) 170 #define MFG_CORE0_PWR_CON (SPM_BASE + 0x34C) 171 #define SYSRAM_CON (SPM_BASE + 0x350) 172 #define SYSROM_CON (SPM_BASE + 0x354) 173 #define SSPM_SRAM_CON (SPM_BASE + 0x358) 174 #define SCP_SRAM_CON (SPM_BASE + 0x35C) 175 #define UFS_SRAM_CON (SPM_BASE + 0x36C) 176 #define DUMMY_SRAM_CON (SPM_BASE + 0x380) 177 #define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x390) 178 #define MD_SRAM_ISO_CON (SPM_BASE + 0x394) 179 #define MD_EXTRA_PWR_CON (SPM_BASE + 0x398) 180 #define EXT_BUCK_CON (SPM_BASE + 0x3A0) 181 #define MBIST_EFUSE_REPAIR_ACK_STA (SPM_BASE + 0x3D0) 182 #define SPM_DVFS_CON (SPM_BASE + 0x400) 183 #define SPM_MDBSI_CON (SPM_BASE + 0x404) 184 #define SPM_MAS_PAUSE_MASK_B (SPM_BASE + 0x408) 185 #define SPM_MAS_PAUSE2_MASK_B (SPM_BASE + 0x40C) 186 #define SPM_BSI_GEN (SPM_BASE + 0x410) 187 #define SPM_BSI_EN_SR (SPM_BASE + 0x414) 188 #define SPM_BSI_CLK_SR (SPM_BASE + 0x418) 189 #define SPM_BSI_D0_SR (SPM_BASE + 0x41C) 190 #define SPM_BSI_D1_SR (SPM_BASE + 0x420) 191 #define SPM_BSI_D2_SR (SPM_BASE + 0x424) 192 #define SPM_AP_SEMA (SPM_BASE + 0x428) 193 #define SPM_SPM_SEMA (SPM_BASE + 0x42C) 194 #define AP_MDSRC_REQ (SPM_BASE + 0x430) 195 #define SPM2MD_DVFS_CON (SPM_BASE + 0x438) 196 #define MD2SPM_DVFS_CON (SPM_BASE + 0x43C) 197 #define DRAMC_DPY_CLK_SW_CON_RSV (SPM_BASE + 0x440) 198 #define DPY_LP_CON (SPM_BASE + 0x444) 199 #define CPU_DVFS_REQ (SPM_BASE + 0x448) 200 #define SPM_PLL_CON (SPM_BASE + 0x44C) 201 #define SPM_EMI_BW_MODE (SPM_BASE + 0x450) 202 #define AP2MD_PEER_WAKEUP (SPM_BASE + 0x454) 203 #define ULPOSC_CON (SPM_BASE + 0x458) 204 #define SPM2MM_CON (SPM_BASE + 0x45C) 205 #define DRAMC_DPY_CLK_SW_CON_SEL (SPM_BASE + 0x460) 206 #define DRAMC_DPY_CLK_SW_CON (SPM_BASE + 0x464) 207 #define SPM_S1_MODE_CH (SPM_BASE + 0x468) 208 #define EMI_SELF_REFRESH_CH_STA (SPM_BASE + 0x46C) 209 #define DRAMC_DPY_CLK_SW_CON_SEL2 (SPM_BASE + 0x470) 210 #define DRAMC_DPY_CLK_SW_CON2 (SPM_BASE + 0x474) 211 #define DRAMC_DMYRD_CON (SPM_BASE + 0x478) 212 #define SPM_DRS_CON (SPM_BASE + 0x47C) 213 #define SPM_SEMA_M0 (SPM_BASE + 0x480) 214 #define SPM_SEMA_M1 (SPM_BASE + 0x484) 215 #define SPM_SEMA_M2 (SPM_BASE + 0x488) 216 #define SPM_SEMA_M3 (SPM_BASE + 0x48C) 217 #define SPM_SEMA_M4 (SPM_BASE + 0x490) 218 #define SPM_SEMA_M5 (SPM_BASE + 0x494) 219 #define SPM_SEMA_M6 (SPM_BASE + 0x498) 220 #define SPM_SEMA_M7 (SPM_BASE + 0x49C) 221 #define SPM_MAS_PAUSE_MM_MASK_B (SPM_BASE + 0x4A0) 222 #define SPM_MAS_PAUSE_MCU_MASK_B (SPM_BASE + 0x4A4) 223 #define SRAM_DREQ_ACK (SPM_BASE + 0x4AC) 224 #define SRAM_DREQ_CON (SPM_BASE + 0x4B0) 225 #define SRAM_DREQ_CON_SET (SPM_BASE + 0x4B4) 226 #define SRAM_DREQ_CON_CLR (SPM_BASE + 0x4B8) 227 #define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x4BC) 228 #define SPM_SSPM_IRQ (SPM_BASE + 0x4C0) 229 #define SPM2PMCU_INT (SPM_BASE + 0x4C4) 230 #define SPM2PMCU_INT_SET (SPM_BASE + 0x4C8) 231 #define SPM2PMCU_INT_CLR (SPM_BASE + 0x4CC) 232 #define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x4D0) 233 #define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x4D4) 234 #define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x4D8) 235 #define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x4DC) 236 #define PMCU2SPM_INT (SPM_BASE + 0x4E0) 237 #define PMCU2SPM_INT_SET (SPM_BASE + 0x4E4) 238 #define PMCU2SPM_INT_CLR (SPM_BASE + 0x4E8) 239 #define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x4EC) 240 #define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x4F0) 241 #define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x4F4) 242 #define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x4F8) 243 #define PMCU2SPM_CFG (SPM_BASE + 0x4FC) 244 #define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x500) 245 #define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x504) 246 #define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x508) 247 #define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x50C) 248 #define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x510) 249 #define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x514) 250 #define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x518) 251 #define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x51C) 252 #define MP0_CPU0_WFI_EN (SPM_BASE + 0x530) 253 #define MP0_CPU1_WFI_EN (SPM_BASE + 0x534) 254 #define MP0_CPU2_WFI_EN (SPM_BASE + 0x538) 255 #define MP0_CPU3_WFI_EN (SPM_BASE + 0x53C) 256 #define MP1_CPU0_WFI_EN (SPM_BASE + 0x540) 257 #define MP1_CPU1_WFI_EN (SPM_BASE + 0x544) 258 #define MP1_CPU2_WFI_EN (SPM_BASE + 0x548) 259 #define MP1_CPU3_WFI_EN (SPM_BASE + 0x54C) 260 #define MP0_L2CFLUSH (SPM_BASE + 0x554) 261 #define MP1_L2CFLUSH (SPM_BASE + 0x558) 262 #define CPU_PTPOD2_CON (SPM_BASE + 0x560) 263 #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x570) 264 #define ROOT_CORE_ADDR (SPM_BASE + 0x574) 265 #define CPU_SPARE_CON (SPM_BASE + 0x580) 266 #define CPU_SPARE_CON_SET (SPM_BASE + 0x584) 267 #define CPU_SPARE_CON_CLR (SPM_BASE + 0x588) 268 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x5D0) 269 #define SPM2SW_MAILBOX_1 (SPM_BASE + 0x5D4) 270 #define SPM2SW_MAILBOX_2 (SPM_BASE + 0x5D8) 271 #define SPM2SW_MAILBOX_3 (SPM_BASE + 0x5DC) 272 #define SW2SPM_INT (SPM_BASE + 0x5E0) 273 #define SW2SPM_INT_SET (SPM_BASE + 0x5E4) 274 #define SW2SPM_INT_CLR (SPM_BASE + 0x5E8) 275 #define SW2SPM_MAILBOX_0 (SPM_BASE + 0x5EC) 276 #define SW2SPM_MAILBOX_1 (SPM_BASE + 0x5F0) 277 #define SW2SPM_MAILBOX_2 (SPM_BASE + 0x5F4) 278 #define SW2SPM_MAILBOX_3 (SPM_BASE + 0x5F8) 279 #define SW2SPM_CFG (SPM_BASE + 0x5FC) 280 #define SPM_SW_FLAG (SPM_BASE + 0x600) 281 #define SPM_SW_DEBUG (SPM_BASE + 0x604) 282 #define SPM_SW_RSV_0 (SPM_BASE + 0x608) 283 #define SPM_SW_RSV_1 (SPM_BASE + 0x60C) 284 #define SPM_SW_RSV_2 (SPM_BASE + 0x610) 285 #define SPM_SW_RSV_3 (SPM_BASE + 0x614) 286 #define SPM_SW_RSV_4 (SPM_BASE + 0x618) 287 #define SPM_SW_RSV_5 (SPM_BASE + 0x61C) 288 #define SPM_RSV_CON (SPM_BASE + 0x620) 289 #define SPM_RSV_STA (SPM_BASE + 0x624) 290 #define SPM_RSV_CON1 (SPM_BASE + 0x628) 291 #define SPM_RSV_STA1 (SPM_BASE + 0x62C) 292 #define SPM_PASR_DPD_0 (SPM_BASE + 0x630) 293 #define SPM_PASR_DPD_1 (SPM_BASE + 0x634) 294 #define SPM_PASR_DPD_2 (SPM_BASE + 0x638) 295 #define SPM_PASR_DPD_3 (SPM_BASE + 0x63C) 296 #define SPM_SPARE_CON (SPM_BASE + 0x640) 297 #define SPM_SPARE_CON_SET (SPM_BASE + 0x644) 298 #define SPM_SPARE_CON_CLR (SPM_BASE + 0x648) 299 #define SPM_SW_RSV_6 (SPM_BASE + 0x64C) 300 #define SPM_SW_RSV_7 (SPM_BASE + 0x650) 301 #define SPM_SW_RSV_8 (SPM_BASE + 0x654) 302 #define SPM_SW_RSV_9 (SPM_BASE + 0x658) 303 #define SPM_SW_RSV_10 (SPM_BASE + 0x65C) 304 #define SPM_SW_RSV_18 (SPM_BASE + 0x67C) 305 #define SPM_SW_RSV_19 (SPM_BASE + 0x680) 306 #define DVFSRC_EVENT_MASK_CON (SPM_BASE + 0x690) 307 #define DVFSRC_EVENT_FORCE_ON (SPM_BASE + 0x694) 308 #define DVFSRC_EVENT_SEL (SPM_BASE + 0x698) 309 #define SPM_DVFS_EVENT_STA (SPM_BASE + 0x69C) 310 #define SPM_DVFS_EVENT_STA1 (SPM_BASE + 0x6A0) 311 #define SPM_DVFS_LEVEL (SPM_BASE + 0x6A4) 312 #define DVFS_ABORT_STA (SPM_BASE + 0x6A8) 313 #define DVFS_ABORT_OTHERS_MASK (SPM_BASE + 0x6AC) 314 #define SPM_DFS_LEVEL (SPM_BASE + 0x6B0) 315 #define SPM_DVS_LEVEL (SPM_BASE + 0x6B4) 316 #define SPM_DVFS_MISC (SPM_BASE + 0x6B8) 317 #define SPARE_SRC_REQ_MASK (SPM_BASE + 0x6C0) 318 #define SCP_VCORE_LEVEL (SPM_BASE + 0x6C4) 319 #define SC_MM_CK_SEL_CON (SPM_BASE + 0x6C8) 320 #define SPARE_ACK_STA (SPM_BASE + 0x6F0) 321 #define SPARE_ACK_MASK (SPM_BASE + 0x6F4) 322 #define SPM_DVFS_CON1 (SPM_BASE + 0x700) 323 #define SPM_DVFS_CON1_STA (SPM_BASE + 0x704) 324 #define SPM_DVFS_CMD0 (SPM_BASE + 0x710) 325 #define SPM_DVFS_CMD1 (SPM_BASE + 0x714) 326 #define SPM_DVFS_CMD2 (SPM_BASE + 0x718) 327 #define SPM_DVFS_CMD3 (SPM_BASE + 0x71C) 328 #define SPM_DVFS_CMD4 (SPM_BASE + 0x720) 329 #define SPM_DVFS_CMD5 (SPM_BASE + 0x724) 330 #define SPM_DVFS_CMD6 (SPM_BASE + 0x728) 331 #define SPM_DVFS_CMD7 (SPM_BASE + 0x72C) 332 #define SPM_DVFS_CMD8 (SPM_BASE + 0x730) 333 #define SPM_DVFS_CMD9 (SPM_BASE + 0x734) 334 #define SPM_DVFS_CMD10 (SPM_BASE + 0x738) 335 #define SPM_DVFS_CMD11 (SPM_BASE + 0x73C) 336 #define SPM_DVFS_CMD12 (SPM_BASE + 0x740) 337 #define SPM_DVFS_CMD13 (SPM_BASE + 0x744) 338 #define SPM_DVFS_CMD14 (SPM_BASE + 0x748) 339 #define SPM_DVFS_CMD15 (SPM_BASE + 0x74C) 340 #define WDT_LATCH_SPARE0_FIX (SPM_BASE + 0x780) 341 #define WDT_LATCH_SPARE1_FIX (SPM_BASE + 0x784) 342 #define WDT_LATCH_SPARE2_FIX (SPM_BASE + 0x788) 343 #define WDT_LATCH_SPARE3_FIX (SPM_BASE + 0x78C) 344 #define SPARE_ACK_IN_FIX (SPM_BASE + 0x790) 345 #define DCHA_LATCH_RSV0_FIX (SPM_BASE + 0x794) 346 #define DCHB_LATCH_RSV0_FIX (SPM_BASE + 0x798) 347 #define PCM_WDT_LATCH_0 (SPM_BASE + 0x800) 348 #define PCM_WDT_LATCH_1 (SPM_BASE + 0x804) 349 #define PCM_WDT_LATCH_2 (SPM_BASE + 0x808) 350 #define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C) 351 #define PCM_WDT_LATCH_4 (SPM_BASE + 0x810) 352 #define PCM_WDT_LATCH_5 (SPM_BASE + 0x814) 353 #define PCM_WDT_LATCH_6 (SPM_BASE + 0x818) 354 #define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C) 355 #define PCM_WDT_LATCH_8 (SPM_BASE + 0x820) 356 #define PCM_WDT_LATCH_9 (SPM_BASE + 0x824) 357 #define WDT_LATCH_SPARE0 (SPM_BASE + 0x828) 358 #define WDT_LATCH_SPARE1 (SPM_BASE + 0x82C) 359 #define WDT_LATCH_SPARE2 (SPM_BASE + 0x830) 360 #define WDT_LATCH_SPARE3 (SPM_BASE + 0x834) 361 #define PCM_WDT_LATCH_10 (SPM_BASE + 0x838) 362 #define PCM_WDT_LATCH_11 (SPM_BASE + 0x83C) 363 #define DCHA_GATING_LATCH_0 (SPM_BASE + 0x840) 364 #define DCHA_GATING_LATCH_1 (SPM_BASE + 0x844) 365 #define DCHA_GATING_LATCH_2 (SPM_BASE + 0x848) 366 #define DCHA_GATING_LATCH_3 (SPM_BASE + 0x84C) 367 #define DCHA_GATING_LATCH_4 (SPM_BASE + 0x850) 368 #define DCHA_GATING_LATCH_5 (SPM_BASE + 0x854) 369 #define DCHA_GATING_LATCH_6 (SPM_BASE + 0x858) 370 #define DCHA_GATING_LATCH_7 (SPM_BASE + 0x85C) 371 #define DCHB_GATING_LATCH_0 (SPM_BASE + 0x860) 372 #define DCHB_GATING_LATCH_1 (SPM_BASE + 0x864) 373 #define DCHB_GATING_LATCH_2 (SPM_BASE + 0x868) 374 #define DCHB_GATING_LATCH_3 (SPM_BASE + 0x86C) 375 #define DCHB_GATING_LATCH_4 (SPM_BASE + 0x870) 376 #define DCHB_GATING_LATCH_5 (SPM_BASE + 0x874) 377 #define DCHB_GATING_LATCH_6 (SPM_BASE + 0x878) 378 #define DCHB_GATING_LATCH_7 (SPM_BASE + 0x87C) 379 #define DCHA_LATCH_RSV0 (SPM_BASE + 0x880) 380 #define DCHB_LATCH_RSV0 (SPM_BASE + 0x884) 381 #define PCM_WDT_LATCH_12 (SPM_BASE + 0x888) 382 #define PCM_WDT_LATCH_13 (SPM_BASE + 0x88C) 383 #define SPM_PC_TRACE_CON (SPM_BASE + 0x8C0) 384 #define SPM_PC_TRACE_G0 (SPM_BASE + 0x8C4) 385 #define SPM_PC_TRACE_G1 (SPM_BASE + 0x8C8) 386 #define SPM_PC_TRACE_G2 (SPM_BASE + 0x8CC) 387 #define SPM_PC_TRACE_G3 (SPM_BASE + 0x8D0) 388 #define SPM_PC_TRACE_G4 (SPM_BASE + 0x8D4) 389 #define SPM_PC_TRACE_G5 (SPM_BASE + 0x8D8) 390 #define SPM_PC_TRACE_G6 (SPM_BASE + 0x8DC) 391 #define SPM_PC_TRACE_G7 (SPM_BASE + 0x8E0) 392 #define SPM_ACK_CHK_CON (SPM_BASE + 0x900) 393 #define SPM_ACK_CHK_PC (SPM_BASE + 0x904) 394 #define SPM_ACK_CHK_SEL (SPM_BASE + 0x908) 395 #define SPM_ACK_CHK_TIMER (SPM_BASE + 0x90C) 396 #define SPM_ACK_CHK_STA (SPM_BASE + 0x910) 397 #define SPM_ACK_CHK_LATCH (SPM_BASE + 0x914) 398 #define SPM_ACK_CHK_CON2 (SPM_BASE + 0x920) 399 #define SPM_ACK_CHK_PC2 (SPM_BASE + 0x924) 400 #define SPM_ACK_CHK_SEL2 (SPM_BASE + 0x928) 401 #define SPM_ACK_CHK_TIMER2 (SPM_BASE + 0x92C) 402 #define SPM_ACK_CHK_STA2 (SPM_BASE + 0x930) 403 #define SPM_ACK_CHK_LATCH2 (SPM_BASE + 0x934) 404 #define SPM_ACK_CHK_CON3 (SPM_BASE + 0x940) 405 #define SPM_ACK_CHK_PC3 (SPM_BASE + 0x944) 406 #define SPM_ACK_CHK_SEL3 (SPM_BASE + 0x948) 407 #define SPM_ACK_CHK_TIMER3 (SPM_BASE + 0x94C) 408 #define SPM_ACK_CHK_STA3 (SPM_BASE + 0x950) 409 #define SPM_ACK_CHK_LATCH3 (SPM_BASE + 0x954) 410 #define SPM_ACK_CHK_CON4 (SPM_BASE + 0x960) 411 #define SPM_ACK_CHK_PC4 (SPM_BASE + 0x964) 412 #define SPM_ACK_CHK_SEL4 (SPM_BASE + 0x968) 413 #define SPM_ACK_CHK_TIMER4 (SPM_BASE + 0x96C) 414 #define SPM_ACK_CHK_STA4 (SPM_BASE + 0x970) 415 #define SPM_ACK_CHK_LATCH4 (SPM_BASE + 0x974) 416 417 /* POWERON_CONFIG_EN (0x10006000+0x000) */ 418 #define BCLK_CG_EN_LSB (1U << 0) /* 1b */ 419 #define MD_BCLK_CG_EN_LSB (1U << 1) /* 1b */ 420 #define PROJECT_CODE_LSB (1U << 16) /* 16b */ 421 /* SPM_POWER_ON_VAL0 (0x10006000+0x004) */ 422 #define POWER_ON_VAL0_LSB (1U << 0) /* 32b */ 423 /* SPM_POWER_ON_VAL1 (0x10006000+0x008) */ 424 #define POWER_ON_VAL1_LSB (1U << 0) /* 32b */ 425 /* SPM_CLK_CON (0x10006000+0x00C) */ 426 #define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */ 427 #define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */ 428 #define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */ 429 #define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ 430 #define EXT_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */ 431 #define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */ 432 #define CXO32K_REMOVE_EN_MD2_LSB (1U << 10) /* 1b */ 433 #define CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */ 434 #define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ 435 #define SRCLKEN0_EN_LSB (1U << 13) /* 1b */ 436 #define SRCLKEN1_EN_LSB (1U << 14) /* 1b */ 437 #define SCP_DCM_EN_LSB (1U << 15) /* 1b */ 438 #define SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 7b */ 439 #define SYSCLK1_SRC_MASK_B_LSB (1U << 23) /* 7b */ 440 /* SPM_CLK_SETTLE (0x10006000+0x010) */ 441 #define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */ 442 /* SPM_AP_STANDBY_CON (0x10006000+0x014) */ 443 #define WFI_OP_LSB (1U << 0) /* 1b */ 444 #define MP0_CPUTOP_IDLE_MASK_LSB (1U << 1) /* 1b */ 445 #define MP1_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */ 446 #define MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */ 447 #define MM_MASK_B_LSB (1U << 16) /* 2b */ 448 #define MD_DDR_EN_0_DBC_EN_LSB (1U << 18) /* 1b */ 449 #define MD_DDR_EN_1_DBC_EN_LSB (1U << 19) /* 1b */ 450 #define MD_MASK_B_LSB (1U << 20) /* 2b */ 451 #define SSPM_MASK_B_LSB (1U << 22) /* 1b */ 452 #define SCP_MASK_B_LSB (1U << 23) /* 1b */ 453 #define SRCCLKENI_MASK_B_LSB (1U << 24) /* 1b */ 454 #define MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */ 455 #define MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */ 456 #define CONN_DDR_EN_DBC_EN_LSB (1U << 27) /* 1b */ 457 #define CONN_MASK_B_LSB (1U << 28) /* 1b */ 458 #define CONN_APSRC_SEL_LSB (1U << 29) /* 1b */ 459 /* PCM_CON0 (0x10006000+0x018) */ 460 #define PCM_KICK_L_LSB (1U << 0) /* 1b */ 461 #define IM_KICK_L_LSB (1U << 1) /* 1b */ 462 #define PCM_CK_EN_LSB (1U << 2) /* 1b */ 463 #define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ 464 #define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */ 465 #define PCM_SW_RESET_LSB (1U << 15) /* 1b */ 466 #define PROJECT_CODE_LSB (1U << 16) /* 16b */ 467 /* PCM_CON1 (0x10006000+0x01C) */ 468 #define IM_SLAVE_LSB (1U << 0) /* 1b */ 469 #define IM_SLEEP_LSB (1U << 1) /* 1b */ 470 #define MIF_APBEN_LSB (1U << 3) /* 1b */ 471 #define IM_PDN_LSB (1U << 4) /* 1b */ 472 #define PCM_TIMER_EN_LSB (1U << 5) /* 1b */ 473 #define IM_NONRP_EN_LSB (1U << 6) /* 1b */ 474 #define DIS_MIF_PROT_LSB (1U << 7) /* 1b */ 475 #define PCM_WDT_EN_LSB (1U << 8) /* 1b */ 476 #define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */ 477 #define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ 478 #define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ 479 #define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ 480 #define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ 481 #define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ 482 #define PROJECT_CODE_LSB (1U << 16) /* 16b */ 483 /* PCM_IM_PTR (0x10006000+0x020) */ 484 #define PCM_IM_PTR_LSB (1U << 0) /* 32b */ 485 /* PCM_IM_LEN (0x10006000+0x024) */ 486 #define PCM_IM_LEN_LSB (1U << 0) /* 13b */ 487 /* PCM_REG_DATA_INI (0x10006000+0x028) */ 488 #define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */ 489 /* PCM_PWR_IO_EN (0x10006000+0x02C) */ 490 #define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */ 491 #define PCM_RF_SYNC_EN_LSB (1U << 16) /* 8b */ 492 /* PCM_TIMER_VAL (0x10006000+0x030) */ 493 #define PCM_TIMER_VAL_LSB (1U << 0) /* 32b */ 494 /* PCM_WDT_VAL (0x10006000+0x034) */ 495 #define PCM_WDT_VAL_LSB (1U << 0) /* 32b */ 496 /* PCM_IM_HOST_RW_PTR (0x10006000+0x038) */ 497 #define PCM_IM_HOST_RW_PTR_LSB (1U << 0) /* 12b */ 498 #define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */ 499 #define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */ 500 /* PCM_IM_HOST_RW_DAT (0x10006000+0x03C) */ 501 #define PCM_IM_HOST_RW_DAT_LSB (1U << 0) /* 32b */ 502 /* PCM_EVENT_VECTOR0 (0x10006000+0x040) */ 503 #define PCM_EVENT_VECTOR_0_LSB (1U << 0) /* 6b */ 504 #define PCM_EVENT_RESUME_0_LSB (1U << 6) /* 1b */ 505 #define PCM_EVENT_IMMEDIA_0_LSB (1U << 7) /* 1b */ 506 #define PCM_EVENT_VECTPC_0_LSB (1U << 16) /* 11b */ 507 /* PCM_EVENT_VECTOR1 (0x10006000+0x044) */ 508 #define PCM_EVENT_VECTOR_1_LSB (1U << 0) /* 6b */ 509 #define PCM_EVENT_RESUME_1_LSB (1U << 6) /* 1b */ 510 #define PCM_EVENT_IMMEDIA_1_LSB (1U << 7) /* 1b */ 511 #define PCM_EVENT_VECTPC_1_LSB (1U << 16) /* 11b */ 512 /* PCM_EVENT_VECTOR2 (0x10006000+0x048) */ 513 #define PCM_EVENT_VECTOR_2_LSB (1U << 0) /* 6b */ 514 #define PCM_EVENT_RESUME_2_LSB (1U << 6) /* 1b */ 515 #define PCM_EVENT_IMMEDIA_2_LSB (1U << 7) /* 1b */ 516 #define PCM_EVENT_VECTPC_2_LSB (1U << 16) /* 11b */ 517 /* PCM_EVENT_VECTOR3 (0x10006000+0x04C) */ 518 #define PCM_EVENT_VECTOR_3_LSB (1U << 0) /* 6b */ 519 #define PCM_EVENT_RESUME_3_LSB (1U << 6) /* 1b */ 520 #define PCM_EVENT_IMMEDIA_3_LSB (1U << 7) /* 1b */ 521 #define PCM_EVENT_VECTPC_3_LSB (1U << 16) /* 11b */ 522 /* PCM_EVENT_VECTOR4 (0x10006000+0x050) */ 523 #define PCM_EVENT_VECTOR_4_LSB (1U << 0) /* 6b */ 524 #define PCM_EVENT_RESUME_4_LSB (1U << 6) /* 1b */ 525 #define PCM_EVENT_IMMEDIA_4_LSB (1U << 7) /* 1b */ 526 #define PCM_EVENT_VECTPC_4_LSB (1U << 16) /* 11b */ 527 /* PCM_EVENT_VECTOR5 (0x10006000+0x054) */ 528 #define PCM_EVENT_VECTOR_5_LSB (1U << 0) /* 6b */ 529 #define PCM_EVENT_RESUME_5_LSB (1U << 6) /* 1b */ 530 #define PCM_EVENT_IMMEDIA_5_LSB (1U << 7) /* 1b */ 531 #define PCM_EVENT_VECTPC_5_LSB (1U << 16) /* 11b */ 532 /* PCM_EVENT_VECTOR6 (0x10006000+0x058) */ 533 #define PCM_EVENT_VECTOR_6_LSB (1U << 0) /* 6b */ 534 #define PCM_EVENT_RESUME_6_LSB (1U << 6) /* 1b */ 535 #define PCM_EVENT_IMMEDIA_6_LSB (1U << 7) /* 1b */ 536 #define PCM_EVENT_VECTPC_6_LSB (1U << 16) /* 11b */ 537 /* PCM_EVENT_VECTOR7 (0x10006000+0x05C) */ 538 #define PCM_EVENT_VECTOR_7_LSB (1U << 0) /* 6b */ 539 #define PCM_EVENT_RESUME_7_LSB (1U << 6) /* 1b */ 540 #define PCM_EVENT_IMMEDIA_7_LSB (1U << 7) /* 1b */ 541 #define PCM_EVENT_VECTPC_7_LSB (1U << 16) /* 11b */ 542 /* PCM_EVENT_VECTOR8 (0x10006000+0x060) */ 543 #define PCM_EVENT_VECTOR_8_LSB (1U << 0) /* 6b */ 544 #define PCM_EVENT_RESUME_8_LSB (1U << 6) /* 1b */ 545 #define PCM_EVENT_IMMEDIA_8_LSB (1U << 7) /* 1b */ 546 #define PCM_EVENT_VECTPC_8_LSB (1U << 16) /* 11b */ 547 /* PCM_EVENT_VECTOR9 (0x10006000+0x064) */ 548 #define PCM_EVENT_VECTOR_9_LSB (1U << 0) /* 6b */ 549 #define PCM_EVENT_RESUME_9_LSB (1U << 6) /* 1b */ 550 #define PCM_EVENT_IMMEDIA_9_LSB (1U << 7) /* 1b */ 551 #define PCM_EVENT_VECTPC_9_LSB (1U << 16) /* 11b */ 552 /* PCM_EVENT_VECTOR10 (0x10006000+0x068) */ 553 #define PCM_EVENT_VECTOR_10_LSB (1U << 0) /* 6b */ 554 #define PCM_EVENT_RESUME_10_LSB (1U << 6) /* 1b */ 555 #define PCM_EVENT_IMMEDIA_10_LSB (1U << 7) /* 1b */ 556 #define PCM_EVENT_VECTPC_10_LSB (1U << 16) /* 11b */ 557 /* PCM_EVENT_VECTOR11 (0x10006000+0x06C) */ 558 #define PCM_EVENT_VECTOR_11_LSB (1U << 0) /* 6b */ 559 #define PCM_EVENT_RESUME_11_LSB (1U << 6) /* 1b */ 560 #define PCM_EVENT_IMMEDIA_11_LSB (1U << 7) /* 1b */ 561 #define PCM_EVENT_VECTPC_11_LSB (1U << 16) /* 11b */ 562 /* PCM_EVENT_VECTOR12 (0x10006000+0x070) */ 563 #define PCM_EVENT_VECTOR_12_LSB (1U << 0) /* 6b */ 564 #define PCM_EVENT_RESUME_12_LSB (1U << 6) /* 1b */ 565 #define PCM_EVENT_IMMEDIA_12_LSB (1U << 7) /* 1b */ 566 #define PCM_EVENT_VECTPC_12_LSB (1U << 16) /* 11b */ 567 /* PCM_EVENT_VECTOR13 (0x10006000+0x074) */ 568 #define PCM_EVENT_VECTOR_13_LSB (1U << 0) /* 6b */ 569 #define PCM_EVENT_RESUME_13_LSB (1U << 6) /* 1b */ 570 #define PCM_EVENT_IMMEDIA_13_LSB (1U << 7) /* 1b */ 571 #define PCM_EVENT_VECTPC_13_LSB (1U << 16) /* 11b */ 572 /* PCM_EVENT_VECTOR14 (0x10006000+0x078) */ 573 #define PCM_EVENT_VECTOR_14_LSB (1U << 0) /* 6b */ 574 #define PCM_EVENT_RESUME_14_LSB (1U << 6) /* 1b */ 575 #define PCM_EVENT_IMMEDIA_14_LSB (1U << 7) /* 1b */ 576 #define PCM_EVENT_VECTPC_14_LSB (1U << 16) /* 11b */ 577 /* PCM_EVENT_VECTOR15 (0x10006000+0x07C) */ 578 #define PCM_EVENT_VECTOR_15_LSB (1U << 0) /* 6b */ 579 #define PCM_EVENT_RESUME_15_LSB (1U << 6) /* 1b */ 580 #define PCM_EVENT_IMMEDIA_15_LSB (1U << 7) /* 1b */ 581 #define PCM_EVENT_VECTPC_15_LSB (1U << 16) /* 11b */ 582 /* PCM_EVENT_VECTOR_EN (0x10006000+0x080) */ 583 #define PCM_EVENT_VECTOR_EN_LSB (1U << 0) /* 16b */ 584 /* SPM_SRAM_RSV_CON (0x10006000+0x088) */ 585 #define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */ 586 /* SPM_SWINT (0x10006000+0x08C) */ 587 #define SPM_SWINT_LSB (1U << 0) /* 10b */ 588 /* SPM_SWINT_SET (0x10006000+0x090) */ 589 #define SPM_SWINT_SET_LSB (1U << 0) /* 10b */ 590 /* SPM_SWINT_CLR (0x10006000+0x094) */ 591 #define SPM_SWINT_CLR_LSB (1U << 0) /* 10b */ 592 /* SPM_SCP_MAILBOX (0x10006000+0x098) */ 593 #define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */ 594 /* SCP_SPM_MAILBOX (0x10006000+0x09C) */ 595 #define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */ 596 /* SPM_TWAM_CON (0x10006000+0x0A0) */ 597 #define TWAM_ENABLE_LSB (1U << 0) /* 1b */ 598 #define TWAM_SPEED_MODE_ENABLE_LSB (1U << 1) /* 1b */ 599 #define TWAM_SW_RST_LSB (1U << 2) /* 1b */ 600 #define TWAM_MON_TYPE0_LSB (1U << 4) /* 2b */ 601 #define TWAM_MON_TYPE1_LSB (1U << 6) /* 2b */ 602 #define TWAM_MON_TYPE2_LSB (1U << 8) /* 2b */ 603 #define TWAM_MON_TYPE3_LSB (1U << 10) /* 2b */ 604 #define TWAM_SIGNAL_SEL0_LSB (1U << 12) /* 5b */ 605 #define TWAM_SIGNAL_SEL1_LSB (1U << 17) /* 5b */ 606 #define TWAM_SIGNAL_SEL2_LSB (1U << 22) /* 5b */ 607 #define TWAM_SIGNAL_SEL3_LSB (1U << 27) /* 5b */ 608 /* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */ 609 #define TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */ 610 /* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */ 611 #define TWAM_IDLE_SEL_LSB (1U << 0) /* 5b */ 612 /* SPM_SCP_IRQ (0x10006000+0x0AC) */ 613 #define SPM_SCP_IRQ_LSB (1U << 0) /* 1b */ 614 #define SPM_SCP_IRQ_SEL_LSB (1U << 4) /* 1b */ 615 /* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */ 616 #define SPM_CPU_WAKEUP_EVENT_LSB (1U << 0) /* 1b */ 617 /* SPM_IRQ_MASK (0x10006000+0x0B4) */ 618 #define SPM_TWAM_IRQ_MASK_LSB (1U << 2) /* 1b */ 619 #define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */ 620 #define SPM_IRQ_MASK_LSB (1U << 8) /* 10b */ 621 /* SPM_SRC_REQ (0x10006000+0x0B8) */ 622 #define SPM_APSRC_REQ_LSB (1U << 0) /* 1b */ 623 #define SPM_F26M_REQ_LSB (1U << 1) /* 1b */ 624 #define SPM_INFRA_REQ_LSB (1U << 3) /* 1b */ 625 #define SPM_VRF18_REQ_LSB (1U << 4) /* 1b */ 626 #define SPM_DDREN_REQ_LSB (1U << 7) /* 1b */ 627 #define SPM_RSV_SRC_REQ_LSB (1U << 8) /* 3b */ 628 #define SPM_DDREN_2_REQ_LSB (1U << 11) /* 1b */ 629 #define CPU_MD_DVFS_SOP_FORCE_ON_LSB (1U << 16) /* 1b */ 630 /* SPM_SRC_MASK (0x10006000+0x0BC) */ 631 #define CSYSPWREQ_MASK_LSB (1U << 0) /* 1b */ 632 #define CCIF0_MD_EVENT_MASK_B_LSB (1U << 1) /* 1b */ 633 #define CCIF0_AP_EVENT_MASK_B_LSB (1U << 2) /* 1b */ 634 #define CCIF1_MD_EVENT_MASK_B_LSB (1U << 3) /* 1b */ 635 #define CCIF1_AP_EVENT_MASK_B_LSB (1U << 4) /* 1b */ 636 #define CCIF2_MD_EVENT_MASK_B_LSB (1U << 5) /* 1b */ 637 #define CCIF2_AP_EVENT_MASK_B_LSB (1U << 6) /* 1b */ 638 #define CCIF3_MD_EVENT_MASK_B_LSB (1U << 7) /* 1b */ 639 #define CCIF3_AP_EVENT_MASK_B_LSB (1U << 8) /* 1b */ 640 #define MD_SRCCLKENA_0_INFRA_MASK_B_LSB (1U << 9) /* 1b */ 641 #define MD_SRCCLKENA_1_INFRA_MASK_B_LSB (1U << 10) /* 1b */ 642 #define CONN_SRCCLKENA_INFRA_MASK_B_LSB (1U << 11) /* 1b */ 643 #define UFS_INFRA_REQ_MASK_B_LSB (1U << 12) /* 1b */ 644 #define SRCCLKENI_INFRA_MASK_B_LSB (1U << 13) /* 1b */ 645 #define MD_APSRC_REQ_0_INFRA_MASK_B_LSB (1U << 14) /* 1b */ 646 #define MD_APSRC_REQ_1_INFRA_MASK_B_LSB (1U << 15) /* 1b */ 647 #define CONN_APSRCREQ_INFRA_MASK_B_LSB (1U << 16) /* 1b */ 648 #define UFS_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */ 649 #define MD_VRF18_REQ_0_MASK_B_LSB (1U << 18) /* 1b */ 650 #define MD_VRF18_REQ_1_MASK_B_LSB (1U << 19) /* 1b */ 651 #define UFS_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */ 652 #define GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */ 653 #define CONN_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */ 654 #define GCE_APSRC_REQ_MASK_B_LSB (1U << 23) /* 1b */ 655 #define DISP0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */ 656 #define DISP1_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */ 657 #define MFG_REQ_MASK_B_LSB (1U << 26) /* 1b */ 658 #define VDEC_REQ_MASK_B_LSB (1U << 27) /* 1b */ 659 /* SPM_SRC2_MASK (0x10006000+0x0C0) */ 660 #define MD_DDR_EN_0_MASK_B_LSB (1U << 0) /* 1b */ 661 #define MD_DDR_EN_1_MASK_B_LSB (1U << 1) /* 1b */ 662 #define CONN_DDR_EN_MASK_B_LSB (1U << 2) /* 1b */ 663 #define DDREN_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */ 664 #define DDREN_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */ 665 #define DISP0_DDREN_MASK_B_LSB (1U << 5) /* 1b */ 666 #define DISP1_DDREN_MASK_B_LSB (1U << 6) /* 1b */ 667 #define GCE_DDREN_MASK_B_LSB (1U << 7) /* 1b */ 668 #define DDREN_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */ 669 #define DDREN_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */ 670 /* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */ 671 #define SPM_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */ 672 /* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0C8) */ 673 #define SPM_WAKEUP_EVENT_EXT_MASK_LSB (1U << 0) /* 32b */ 674 /* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0CC) */ 675 #define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */ 676 /* SCP_CLK_CON (0x10006000+0x0D0) */ 677 #define SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */ 678 #define SCP_SECURE_V_REQ_MASK_LSB (1U << 1) /* 1b */ 679 #define SCP_SLP_REQ_LSB (1U << 2) /* 1b */ 680 #define SCP_SLP_ACK_LSB (1U << 3) /* 1b */ 681 /* PCM_DEBUG_CON (0x10006000+0x0D4) */ 682 #define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */ 683 /* DDR_EN_DBC_LEN (0x10006000+0x0D8) */ 684 #define MD_DDR_EN_0_DBC_LEN_LSB (1U << 0) /* 10b */ 685 #define MD_DDR_EN_1_DBC_LEN_LSB (1U << 10) /* 10b */ 686 #define CONN_DDR_EN_DBC_LEN_LSB (1U << 20) /* 10b */ 687 /* AHB_BUS_CON (0x10006000+0x0DC) */ 688 #define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */ 689 #define REG_AHB_LOCK_LSB (1U << 8) /* 1b */ 690 /* SPM_SRC3_MASK (0x10006000+0x0E0) */ 691 #define MD_DDR_EN_2_0_MASK_B_LSB (1U << 0) /* 1b */ 692 #define MD_DDR_EN_2_1_MASK_B_LSB (1U << 1) /* 1b */ 693 #define CONN_DDR_EN_2_MASK_B_LSB (1U << 2) /* 1b */ 694 #define DDREN2_SSPM_APSRC_REQ_MASK_B_LSB (1U << 3) /* 1b */ 695 #define DDREN2_SCP_APSRC_REQ_MASK_B_LSB (1U << 4) /* 1b */ 696 #define DISP0_DDREN2_MASK_B_LSB (1U << 5) /* 1b */ 697 #define DISP1_DDREN2_MASK_B_LSB (1U << 6) /* 1b */ 698 #define GCE_DDREN2_MASK_B_LSB (1U << 7) /* 1b */ 699 #define DDREN2_EMI_SELF_REFRESH_CH0_MASK_B_LSB (1U << 8) /* 1b */ 700 #define DDREN2_EMI_SELF_REFRESH_CH1_MASK_B_LSB (1U << 9) /* 1b */ 701 /* DDR_EN_EMI_DBC_CON (0x10006000+0x0E4) */ 702 #define EMI_SELF_REFRESH_CH0_DBC_LEN_LSB (1U << 0) /* 10b */ 703 #define EMI_SELF_REFRESH_CH0_DBC_EN_LSB (1U << 10) /* 1b */ 704 #define EMI_SELF_REFRESH_CH1_DBC_LEN_LSB (1U << 16) /* 10b */ 705 #define EMI_SELF_REFRESH_CH1_DBC_EN_LSB (1U << 26) /* 1b */ 706 /* SSPM_CLK_CON (0x10006000+0x0E8) */ 707 #define SSPM_26M_CK_SEL_LSB (1U << 0) /* 1b */ 708 /* PCM_REG0_DATA (0x10006000+0x100) */ 709 #define PCM_REG0_DATA_LSB (1U << 0) /* 32b */ 710 /* PCM_REG1_DATA (0x10006000+0x104) */ 711 #define PCM_REG1_DATA_LSB (1U << 0) /* 32b */ 712 /* PCM_REG2_DATA (0x10006000+0x108) */ 713 #define PCM_REG2_DATA_LSB (1U << 0) /* 32b */ 714 /* PCM_REG3_DATA (0x10006000+0x10C) */ 715 #define PCM_REG3_DATA_LSB (1U << 0) /* 32b */ 716 /* PCM_REG4_DATA (0x10006000+0x110) */ 717 #define PCM_REG4_DATA_LSB (1U << 0) /* 32b */ 718 /* PCM_REG5_DATA (0x10006000+0x114) */ 719 #define PCM_REG5_DATA_LSB (1U << 0) /* 32b */ 720 /* PCM_REG6_DATA (0x10006000+0x118) */ 721 #define PCM_REG6_DATA_LSB (1U << 0) /* 32b */ 722 /* PCM_REG7_DATA (0x10006000+0x11C) */ 723 #define PCM_REG7_DATA_LSB (1U << 0) /* 32b */ 724 /* PCM_REG8_DATA (0x10006000+0x120) */ 725 #define PCM_REG8_DATA_LSB (1U << 0) /* 32b */ 726 /* PCM_REG9_DATA (0x10006000+0x124) */ 727 #define PCM_REG9_DATA_LSB (1U << 0) /* 32b */ 728 /* PCM_REG10_DATA (0x10006000+0x128) */ 729 #define PCM_REG10_DATA_LSB (1U << 0) /* 32b */ 730 /* PCM_REG11_DATA (0x10006000+0x12C) */ 731 #define PCM_REG11_DATA_LSB (1U << 0) /* 32b */ 732 /* PCM_REG12_DATA (0x10006000+0x130) */ 733 #define PCM_REG12_DATA_LSB (1U << 0) /* 32b */ 734 /* PCM_REG13_DATA (0x10006000+0x134) */ 735 #define PCM_REG13_DATA_LSB (1U << 0) /* 32b */ 736 /* PCM_REG14_DATA (0x10006000+0x138) */ 737 #define PCM_REG14_DATA_LSB (1U << 0) /* 32b */ 738 /* PCM_REG15_DATA (0x10006000+0x13C) */ 739 #define PCM_REG15_DATA_LSB (1U << 0) /* 32b */ 740 /* PCM_REG12_MASK_B_STA (0x10006000+0x140) */ 741 #define PCM_REG12_MASK_B_STA_LSB (1U << 0) /* 32b */ 742 /* PCM_REG12_EXT_DATA (0x10006000+0x144) */ 743 #define PCM_REG12_EXT_DATA_LSB (1U << 0) /* 32b */ 744 /* PCM_REG12_EXT_MASK_B_STA (0x10006000+0x148) */ 745 #define PCM_REG12_EXT_MASK_B_STA_LSB (1U << 0) /* 32b */ 746 /* PCM_EVENT_REG_STA (0x10006000+0x14C) */ 747 #define PCM_EVENT_REG_STA_LSB (1U << 0) /* 32b */ 748 /* PCM_TIMER_OUT (0x10006000+0x150) */ 749 #define PCM_TIMER_OUT_LSB (1U << 0) /* 32b */ 750 /* PCM_WDT_OUT (0x10006000+0x154) */ 751 #define PCM_WDT_OUT_LSB (1U << 0) /* 32b */ 752 /* SPM_IRQ_STA (0x10006000+0x158) */ 753 #define SPM_ACK_CHK_WAKEUP_LSB (1U << 1) /* 1b */ 754 #define TWAM_IRQ_LSB (1U << 2) /* 1b */ 755 #define PCM_IRQ_LSB (1U << 3) /* 1b */ 756 /* #define SPM_SWINT_LSB (1U << 4) */ /* 10b */ 757 /* SPM_WAKEUP_STA (0x10006000+0x15C) */ 758 #define SPM_WAKEUP_EVENT_STA_LSB (1U << 0) /* 32b */ 759 /* SPM_WAKEUP_EXT_STA (0x10006000+0x160) */ 760 #define SPM_WAKEUP_EVENT_EXT_STA_LSB (1U << 0) /* 32b */ 761 /* SPM_WAKEUP_MISC (0x10006000+0x164) */ 762 #define SPM_WAKEUP_EVENT_MISC_LSB (1U << 0) /* 30b */ 763 #define SPM_PWRAP_IRQ_ACK_LSB (1U << 30) /* 1b */ 764 #define SPM_PWRAP_IRQ_LSB (1U << 31) /* 1b */ 765 /* BUS_PROTECT_RDY (0x10006000+0x168) */ 766 #define BUS_PROTECT_RDY_LSB (1U << 0) /* 32b */ 767 /* BUS_PROTECT2_RDY (0x10006000+0x16C) */ 768 #define BUS_PROTECT2_RDY_LSB (1U << 0) /* 32b */ 769 /* SUBSYS_IDLE_STA (0x10006000+0x170) */ 770 #define SUBSYS_IDLE_STA_LSB (1U << 0) /* 32b */ 771 /* CPU_IDLE_STA (0x10006000+0x174) */ 772 #define MP0_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 0) /* 1b */ 773 #define MP0_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 1) /* 1b */ 774 #define MP0_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 2) /* 1b */ 775 #define MP0_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 3) /* 1b */ 776 #define MP1_CPU0_STANDBYWFI_AFTER_SEL_LSB (1U << 4) /* 1b */ 777 #define MP1_CPU1_STANDBYWFI_AFTER_SEL_LSB (1U << 5) /* 1b */ 778 #define MP1_CPU2_STANDBYWFI_AFTER_SEL_LSB (1U << 6) /* 1b */ 779 #define MP1_CPU3_STANDBYWFI_AFTER_SEL_LSB (1U << 7) /* 1b */ 780 #define MP0_CPU0_STANDBYWFI_LSB (1U << 10) /* 1b */ 781 #define MP0_CPU1_STANDBYWFI_LSB (1U << 11) /* 1b */ 782 #define MP0_CPU2_STANDBYWFI_LSB (1U << 12) /* 1b */ 783 #define MP0_CPU3_STANDBYWFI_LSB (1U << 13) /* 1b */ 784 #define MP1_CPU0_STANDBYWFI_LSB (1U << 14) /* 1b */ 785 #define MP1_CPU1_STANDBYWFI_LSB (1U << 15) /* 1b */ 786 #define MP1_CPU2_STANDBYWFI_LSB (1U << 16) /* 1b */ 787 #define MP1_CPU3_STANDBYWFI_LSB (1U << 17) /* 1b */ 788 #define MP0_CPUTOP_IDLE_LSB (1U << 20) /* 1b */ 789 #define MP1_CPUTOP_IDLE_LSB (1U << 21) /* 1b */ 790 #define MCU_BIU_IDLE_LSB (1U << 22) /* 1b */ 791 #define MCUSYS_IDLE_LSB (1U << 23) /* 1b */ 792 /* PCM_FSM_STA (0x10006000+0x178) */ 793 #define EXEC_INST_OP_LSB (1U << 0) /* 4b */ 794 #define PC_STATE_LSB (1U << 4) /* 3b */ 795 #define IM_STATE_LSB (1U << 7) /* 3b */ 796 #define MASTER_STATE_LSB (1U << 10) /* 5b */ 797 #define EVENT_FSM_LSB (1U << 15) /* 3b */ 798 #define PCM_CLK_SEL_STA_LSB (1U << 18) /* 3b */ 799 #define PCM_KICK_LSB (1U << 21) /* 1b */ 800 #define IM_KICK_LSB (1U << 22) /* 1b */ 801 #define EXT_SRCCLKEN_STA_LSB (1U << 23) /* 2b */ 802 #define EXT_SRCVOLTEN_STA_LSB (1U << 25) /* 1b */ 803 /* SRC_REQ_STA (0x10006000+0x17C) */ 804 #define SRC_REQ_STA_LSB (1U << 0) /* 32b */ 805 /* PWR_STATUS (0x10006000+0x180) */ 806 #define PWR_STATUS_LSB (1U << 0) /* 32b */ 807 /* PWR_STATUS_2ND (0x10006000+0x184) */ 808 #define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ 809 /* CPU_PWR_STATUS (0x10006000+0x188) */ 810 #define CPU_PWR_STATUS_LSB (1U << 0) /* 32b */ 811 /* CPU_PWR_STATUS_2ND (0x10006000+0x18C) */ 812 #define CPU_PWR_STATUS_2ND_LSB (1U << 0) /* 32b */ 813 /* MISC_STA (0x10006000+0x190) */ 814 #define MM_DVFS_HALT_AF_MASK_LSB (1U << 0) /* 5b */ 815 /* SPM_SRC_RDY_STA (0x10006000+0x194) */ 816 #define SPM_INFRA_SRC_ACK_LSB (1U << 0) /* 1b */ 817 #define SPM_VRF18_SRC_ACK_LSB (1U << 1) /* 1b */ 818 /* DRAMC_DBG_LATCH (0x10006000+0x19C) */ 819 #define DRAMC_DEBUG_LATCH_STATUS_LSB (1U << 0) /* 32b */ 820 /* SPM_TWAM_LAST_STA0 (0x10006000+0x1A0) */ 821 #define SPM_TWAM_LAST_STA0_LSB (1U << 0) /* 32b */ 822 /* SPM_TWAM_LAST_STA1 (0x10006000+0x1A4) */ 823 #define SPM_TWAM_LAST_STA1_LSB (1U << 0) /* 32b */ 824 /* SPM_TWAM_LAST_STA2 (0x10006000+0x1A8) */ 825 #define SPM_TWAM_LAST_STA2_LSB (1U << 0) /* 32b */ 826 /* SPM_TWAM_LAST_STA3 (0x10006000+0x1AC) */ 827 #define SPM_TWAM_LAST_STA3_LSB (1U << 0) /* 32b */ 828 /* SPM_TWAM_CURR_STA0 (0x10006000+0x1B0) */ 829 #define SPM_TWAM_CURR_STA0_LSB (1U << 0) /* 32b */ 830 /* SPM_TWAM_CURR_STA1 (0x10006000+0x1B4) */ 831 #define SPM_TWAM_CURR_STA1_LSB (1U << 0) /* 32b */ 832 /* SPM_TWAM_CURR_STA2 (0x10006000+0x1B8) */ 833 #define SPM_TWAM_CURR_STA2_LSB (1U << 0) /* 32b */ 834 /* SPM_TWAM_CURR_STA3 (0x10006000+0x1BC) */ 835 #define SPM_TWAM_CURR_STA3_LSB (1U << 0) /* 32b */ 836 /* SPM_TWAM_TIMER_OUT (0x10006000+0x1C0) */ 837 #define SPM_TWAM_TIMER_OUT_LSB (1U << 0) /* 32b */ 838 /* SPM_DVFS_STA (0x10006000+0x1C8) */ 839 #define MD_DVFS_ERROR_STATUS_LSB (1U << 0) /* 1b */ 840 /* BUS_PROTECT3_RDY (0x10006000+0x1CC) */ 841 #define BUS_PROTECT_MM_RDY_LSB (1U << 0) /* 16b */ 842 #define BUS_PROTECT_MCU_RDY_LSB (1U << 16) /* 16b */ 843 /* SRC_DDREN_STA (0x10006000+0x1E0) */ 844 #define SRC_DDREN_STA_LSB (1U << 0) /* 32b */ 845 /* MCU_PWR_CON (0x10006000+0x200) */ 846 #define MCU_PWR_RST_B_LSB (1U << 0) /* 1b */ 847 #define MCU_PWR_ISO_LSB (1U << 1) /* 1b */ 848 #define MCU_PWR_ON_LSB (1U << 2) /* 1b */ 849 #define MCU_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 850 #define MCU_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 851 #define MCU_SRAM_CKISO_LSB (1U << 5) /* 1b */ 852 #define MCU_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 853 #define MCU_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 854 #define MCU_SRAM_PDN_LSB (1U << 8) /* 1b */ 855 #define MCU_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 856 #define SC_MCU_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 857 #define SC_MCU_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 858 /* MP0_CPUTOP_PWR_CON (0x10006000+0x204) */ 859 #define MP0_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ 860 #define MP0_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ 861 #define MP0_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ 862 #define MP0_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 863 #define MP0_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 864 #define MP0_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ 865 #define MP0_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 866 #define MP0_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 867 #define MP0_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ 868 #define MP0_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 869 #define SC_MP0_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 870 #define SC_MP0_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 871 /* MP0_CPU0_PWR_CON (0x10006000+0x208) */ 872 #define MP0_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ 873 #define MP0_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ 874 #define MP0_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ 875 #define MP0_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 876 #define MP0_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 877 #define MP0_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ 878 #define MP0_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 879 #define MP0_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 880 #define MP0_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ 881 #define MP0_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 882 #define SC_MP0_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 883 #define SC_MP0_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 884 /* MP0_CPU1_PWR_CON (0x10006000+0x20C) */ 885 #define MP0_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ 886 #define MP0_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ 887 #define MP0_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ 888 #define MP0_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 889 #define MP0_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 890 #define MP0_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ 891 #define MP0_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 892 #define MP0_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 893 #define MP0_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ 894 #define MP0_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 895 #define SC_MP0_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 896 #define SC_MP0_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 897 /* MP0_CPU2_PWR_CON (0x10006000+0x210) */ 898 #define MP0_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ 899 #define MP0_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ 900 #define MP0_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ 901 #define MP0_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 902 #define MP0_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 903 #define MP0_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ 904 #define MP0_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 905 #define MP0_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 906 #define MP0_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ 907 #define MP0_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 908 #define SC_MP0_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 909 #define SC_MP0_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 910 /* MP0_CPU3_PWR_CON (0x10006000+0x214) */ 911 #define MP0_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ 912 #define MP0_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ 913 #define MP0_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ 914 #define MP0_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 915 #define MP0_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 916 #define MP0_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ 917 #define MP0_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 918 #define MP0_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 919 #define MP0_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ 920 #define MP0_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 921 #define SC_MP0_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 922 #define SC_MP0_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 923 /* MP1_CPUTOP_PWR_CON (0x10006000+0x218) */ 924 #define MP1_CPUTOP_PWR_RST_B_LSB (1U << 0) /* 1b */ 925 #define MP1_CPUTOP_PWR_ISO_LSB (1U << 1) /* 1b */ 926 #define MP1_CPUTOP_PWR_ON_LSB (1U << 2) /* 1b */ 927 #define MP1_CPUTOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 928 #define MP1_CPUTOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 929 #define MP1_CPUTOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ 930 #define MP1_CPUTOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 931 #define MP1_CPUTOP_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 932 #define MP1_CPUTOP_SRAM_PDN_LSB (1U << 8) /* 1b */ 933 #define MP1_CPUTOP_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 934 #define SC_MP1_CPUTOP_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 935 #define SC_MP1_CPUTOP_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 936 /* MP1_CPU0_PWR_CON (0x10006000+0x21C) */ 937 #define MP1_CPU0_PWR_RST_B_LSB (1U << 0) /* 1b */ 938 #define MP1_CPU0_PWR_ISO_LSB (1U << 1) /* 1b */ 939 #define MP1_CPU0_PWR_ON_LSB (1U << 2) /* 1b */ 940 #define MP1_CPU0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 941 #define MP1_CPU0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 942 #define MP1_CPU0_SRAM_CKISO_LSB (1U << 5) /* 1b */ 943 #define MP1_CPU0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 944 #define MP1_CPU0_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 945 #define MP1_CPU0_SRAM_PDN_LSB (1U << 8) /* 1b */ 946 #define MP1_CPU0_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 947 #define SC_MP1_CPU0_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 948 #define SC_MP1_CPU0_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 949 /* MP1_CPU1_PWR_CON (0x10006000+0x220) */ 950 #define MP1_CPU1_PWR_RST_B_LSB (1U << 0) /* 1b */ 951 #define MP1_CPU1_PWR_ISO_LSB (1U << 1) /* 1b */ 952 #define MP1_CPU1_PWR_ON_LSB (1U << 2) /* 1b */ 953 #define MP1_CPU1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 954 #define MP1_CPU1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 955 #define MP1_CPU1_SRAM_CKISO_LSB (1U << 5) /* 1b */ 956 #define MP1_CPU1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 957 #define MP1_CPU1_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 958 #define MP1_CPU1_SRAM_PDN_LSB (1U << 8) /* 1b */ 959 #define MP1_CPU1_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 960 #define SC_MP1_CPU1_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 961 #define SC_MP1_CPU1_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 962 /* MP1_CPU2_PWR_CON (0x10006000+0x224) */ 963 #define MP1_CPU2_PWR_RST_B_LSB (1U << 0) /* 1b */ 964 #define MP1_CPU2_PWR_ISO_LSB (1U << 1) /* 1b */ 965 #define MP1_CPU2_PWR_ON_LSB (1U << 2) /* 1b */ 966 #define MP1_CPU2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 967 #define MP1_CPU2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 968 #define MP1_CPU2_SRAM_CKISO_LSB (1U << 5) /* 1b */ 969 #define MP1_CPU2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 970 #define MP1_CPU2_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 971 #define MP1_CPU2_SRAM_PDN_LSB (1U << 8) /* 1b */ 972 #define MP1_CPU2_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 973 #define SC_MP1_CPU2_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 974 #define SC_MP1_CPU2_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 975 /* MP1_CPU3_PWR_CON (0x10006000+0x228) */ 976 #define MP1_CPU3_PWR_RST_B_LSB (1U << 0) /* 1b */ 977 #define MP1_CPU3_PWR_ISO_LSB (1U << 1) /* 1b */ 978 #define MP1_CPU3_PWR_ON_LSB (1U << 2) /* 1b */ 979 #define MP1_CPU3_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 980 #define MP1_CPU3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 981 #define MP1_CPU3_SRAM_CKISO_LSB (1U << 5) /* 1b */ 982 #define MP1_CPU3_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 983 #define MP1_CPU3_SRAM_PD_SLPB_CLAMP_LSB (1U << 7) /* 1b */ 984 #define MP1_CPU3_SRAM_PDN_LSB (1U << 8) /* 1b */ 985 #define MP1_CPU3_SRAM_SLEEP_B_LSB (1U << 12) /* 1b */ 986 #define SC_MP1_CPU3_SRAM_PDN_ACK_LSB (1U << 24) /* 1b */ 987 #define SC_MP1_CPU3_SRAM_SLEEP_B_ACK_LSB (1U << 28) /* 1b */ 988 /* MP0_CPUTOP_L2_PDN (0x10006000+0x240) */ 989 #define MP0_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ 990 #define MP0_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ 991 /* MP0_CPUTOP_L2_SLEEP_B (0x10006000+0x244) */ 992 #define MP0_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ 993 #define MP0_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ 994 /* MP0_CPU0_L1_PDN (0x10006000+0x248) */ 995 #define MP0_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ 996 #define MP0_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 997 /* MP0_CPU1_L1_PDN (0x10006000+0x24C) */ 998 #define MP0_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ 999 #define MP0_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1000 /* MP0_CPU2_L1_PDN (0x10006000+0x250) */ 1001 #define MP0_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ 1002 #define MP0_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1003 /* MP0_CPU3_L1_PDN (0x10006000+0x254) */ 1004 #define MP0_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ 1005 #define MP0_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1006 /* MP1_CPUTOP_L2_PDN (0x10006000+0x258) */ 1007 #define MP1_CPUTOP_L2_SRAM_PDN_LSB (1U << 0) /* 1b */ 1008 #define MP1_CPUTOP_L2_SRAM_PDN_ACK_LSB (1U << 8) /* 1b */ 1009 /* MP1_CPUTOP_L2_SLEEP_B (0x10006000+0x25C) */ 1010 #define MP1_CPUTOP_L2_SRAM_SLEEP_B_LSB (1U << 0) /* 1b */ 1011 #define MP1_CPUTOP_L2_SRAM_SLEEP_B_ACK_LSB (1U << 8) /* 1b */ 1012 /* MP1_CPU0_L1_PDN (0x10006000+0x260) */ 1013 #define MP1_CPU0_L1_PDN_LSB (1U << 0) /* 1b */ 1014 #define MP1_CPU0_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1015 /* MP1_CPU1_L1_PDN (0x10006000+0x264) */ 1016 #define MP1_CPU1_L1_PDN_LSB (1U << 0) /* 1b */ 1017 #define MP1_CPU1_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1018 /* MP1_CPU2_L1_PDN (0x10006000+0x268) */ 1019 #define MP1_CPU2_L1_PDN_LSB (1U << 0) /* 1b */ 1020 #define MP1_CPU2_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1021 /* MP1_CPU3_L1_PDN (0x10006000+0x26C) */ 1022 #define MP1_CPU3_L1_PDN_LSB (1U << 0) /* 1b */ 1023 #define MP1_CPU3_L1_PDN_ACK_LSB (1U << 8) /* 1b */ 1024 /* CPU_EXT_BUCK_ISO (0x10006000+0x290) */ 1025 #define MP0_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */ 1026 #define MP1_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */ 1027 #define MP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */ 1028 /* DUMMY1_PWR_CON (0x10006000+0x2B0) */ 1029 #define DUMMY1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1030 #define DUMMY1_PWR_ISO_LSB (1U << 1) /* 1b */ 1031 #define DUMMY1_PWR_ON_LSB (1U << 2) /* 1b */ 1032 #define DUMMY1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1033 #define DUMMY1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1034 /* BYPASS_SPMC (0x10006000+0x2B4) */ 1035 #define BYPASS_CPU_SPMC_MODE_LSB (1U << 0) /* 1b */ 1036 /* SPMC_DORMANT_ENABLE (0x10006000+0x2B8) */ 1037 #define MP0_SPMC_SRAM_DORMANT_EN_LSB (1U << 0) /* 1b */ 1038 #define MP1_SPMC_SRAM_DORMANT_EN_LSB (1U << 1) /* 1b */ 1039 /* ARMPLL_CLK_CON (0x10006000+0x2BC) */ 1040 #define REG_SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 3b */ 1041 #define REG_SC_ARM_CLK_OFF_LSB (1U << 3) /* 3b */ 1042 #define REG_SC_ARMPLLOUT_OFF_LSB (1U << 6) /* 3b */ 1043 #define REG_SC_ARMPLL_OFF_LSB (1U << 9) /* 3b */ 1044 #define REG_SC_ARMPLL_S_OFF_LSB (1U << 12) /* 3b */ 1045 /* SPMC_IN_RET (0x10006000+0x2C0) */ 1046 #define SPMC_STATUS_LSB (1U << 0) /* 8b */ 1047 /* VDE_PWR_CON (0x10006000+0x300) */ 1048 #define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */ 1049 #define VDE_PWR_ISO_LSB (1U << 1) /* 1b */ 1050 #define VDE_PWR_ON_LSB (1U << 2) /* 1b */ 1051 #define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1052 #define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1053 #define VDE_SRAM_PDN_LSB (1U << 8) /* 4b */ 1054 #define VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1055 /* VEN_PWR_CON (0x10006000+0x304) */ 1056 #define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */ 1057 #define VEN_PWR_ISO_LSB (1U << 1) /* 1b */ 1058 #define VEN_PWR_ON_LSB (1U << 2) /* 1b */ 1059 #define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1060 #define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1061 #define VEN_SRAM_PDN_LSB (1U << 8) /* 4b */ 1062 #define VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1063 /* ISP_PWR_CON (0x10006000+0x308) */ 1064 #define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1065 #define ISP_PWR_ISO_LSB (1U << 1) /* 1b */ 1066 #define ISP_PWR_ON_LSB (1U << 2) /* 1b */ 1067 #define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1068 #define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1069 #define ISP_SRAM_PDN_LSB (1U << 8) /* 4b */ 1070 #define ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1071 /* DIS_PWR_CON (0x10006000+0x30C) */ 1072 #define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */ 1073 #define DIS_PWR_ISO_LSB (1U << 1) /* 1b */ 1074 #define DIS_PWR_ON_LSB (1U << 2) /* 1b */ 1075 #define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1076 #define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1077 #define DIS_SRAM_PDN_LSB (1U << 8) /* 4b */ 1078 #define DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1079 /* MFG_CORE1_PWR_CON (0x10006000+0x310) */ 1080 #define MFG_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1081 #define MFG_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ 1082 #define MFG_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ 1083 #define MFG_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1084 #define MFG_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1085 #define MFG_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */ 1086 #define MFG_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1087 /* AUDIO_PWR_CON (0x10006000+0x314) */ 1088 #define AUD_PWR_RST_B_LSB (1U << 0) /* 1b */ 1089 #define AUD_PWR_ISO_LSB (1U << 1) /* 1b */ 1090 #define AUD_PWR_ON_LSB (1U << 2) /* 1b */ 1091 #define AUD_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1092 #define AUD_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1093 #define AUD_SRAM_PDN_LSB (1U << 8) /* 4b */ 1094 #define AUD_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1095 /* IFR_PWR_CON (0x10006000+0x318) */ 1096 #define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */ 1097 #define IFR_PWR_ISO_LSB (1U << 1) /* 1b */ 1098 #define IFR_PWR_ON_LSB (1U << 2) /* 1b */ 1099 #define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1100 #define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1101 #define IFR_SRAM_PDN_LSB (1U << 8) /* 4b */ 1102 #define IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1103 /* DPY_PWR_CON (0x10006000+0x31C) */ 1104 #define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */ 1105 #define DPY_PWR_ISO_LSB (1U << 1) /* 1b */ 1106 #define DPY_PWR_ON_LSB (1U << 2) /* 1b */ 1107 #define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1108 #define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1109 #define DPY_SRAM_PDN_LSB (1U << 8) /* 4b */ 1110 #define DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1111 /* MD1_PWR_CON (0x10006000+0x320) */ 1112 #define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1113 #define MD1_PWR_ISO_LSB (1U << 1) /* 1b */ 1114 #define MD1_PWR_ON_LSB (1U << 2) /* 1b */ 1115 #define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1116 #define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1117 #define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */ 1118 /* VPU_TOP_PWR_CON (0x10006000+0x324) */ 1119 #define VPU_TOP_PWR_RST_B_LSB (1U << 0) /* 1b */ 1120 #define VPU_TOP_PWR_ISO_LSB (1U << 1) /* 1b */ 1121 #define VPU_TOP_PWR_ON_LSB (1U << 2) /* 1b */ 1122 #define VPU_TOP_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1123 #define VPU_TOP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1124 #define VPU_TOP_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1125 #define VPU_TOP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1126 #define VPU_TOP_SRAM_PDN_LSB (1U << 8) /* 4b */ 1127 #define VPU_TOP_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1128 #define VPU_TOP_SRAM_SLPB_LSB (1U << 16) /* 4b */ 1129 #define VPU_TOP_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ 1130 /* CONN_PWR_CON (0x10006000+0x32C) */ 1131 #define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */ 1132 #define CONN_PWR_ISO_LSB (1U << 1) /* 1b */ 1133 #define CONN_PWR_ON_LSB (1U << 2) /* 1b */ 1134 #define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1135 #define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1136 #define CONN_SRAM_PDN_LSB (1U << 8) /* 1b */ 1137 #define CONN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */ 1138 /* VPU_CORE2_PWR_CON (0x10006000+0x330) */ 1139 #define VPU_CORE2_PWR_RST_B_LSB (1U << 0) /* 1b */ 1140 #define VPU_CORE2_PWR_ISO_LSB (1U << 1) /* 1b */ 1141 #define VPU_CORE2_PWR_ON_LSB (1U << 2) /* 1b */ 1142 #define VPU_CORE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1143 #define VPU_CORE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1144 #define VPU_CORE2_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1145 #define VPU_CORE2_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1146 #define VPU_CORE2_SRAM_PDN_LSB (1U << 8) /* 4b */ 1147 #define VPU_CORE2_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1148 #define VPU_CORE2_SRAM_SLPB_LSB (1U << 16) /* 4b */ 1149 #define VPU_CORE2_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ 1150 /* MFG_ASYNC_PWR_CON (0x10006000+0x334) */ 1151 #define MFG_ASYNC_PWR_RST_B_LSB (1U << 0) /* 1b */ 1152 #define MFG_ASYNC_PWR_ISO_LSB (1U << 1) /* 1b */ 1153 #define MFG_ASYNC_PWR_ON_LSB (1U << 2) /* 1b */ 1154 #define MFG_ASYNC_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1155 #define MFG_ASYNC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1156 #define MFG_ASYNC_SRAM_PDN_LSB (1U << 8) /* 4b */ 1157 #define MFG_ASYNC_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1158 /* MFG_PWR_CON (0x10006000+0x338) */ 1159 #define MFG_PWR_RST_B_LSB (1U << 0) /* 1b */ 1160 #define MFG_PWR_ISO_LSB (1U << 1) /* 1b */ 1161 #define MFG_PWR_ON_LSB (1U << 2) /* 1b */ 1162 #define MFG_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1163 #define MFG_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1164 #define MFG_SRAM_PDN_LSB (1U << 8) /* 4b */ 1165 #define MFG_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1166 /* VPU_CORE0_PWR_CON (0x10006000+0x33C) */ 1167 #define VPU_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ 1168 #define VPU_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ 1169 #define VPU_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ 1170 #define VPU_CORE0_ON_2ND_LSB (1U << 3) /* 1b */ 1171 #define VPU_CORE0_CLK_DIS_LSB (1U << 4) /* 1b */ 1172 #define VPU_CORE0_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1173 #define VPU_CORE0_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1174 #define VPU_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */ 1175 #define VPU_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1176 #define VPU_CORE0_SRAM_SLPB_LSB (1U << 16) /* 4b */ 1177 #define VPU_CORE0_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ 1178 /* VPU_CORE1_PWR_CON (0x10006000+0x340) */ 1179 #define VPU_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */ 1180 #define VPU_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */ 1181 #define VPU_CORE1_PWR_ON_LSB (1U << 2) /* 1b */ 1182 #define VPU_CORE1_ON_2ND_LSB (1U << 3) /* 1b */ 1183 #define VPU_CORE1_CLK_DIS_LSB (1U << 4) /* 1b */ 1184 #define VPU_CORE1_SRAM_CKISO_LSB (1U << 5) /* 1b */ 1185 #define VPU_CORE1_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */ 1186 #define VPU_CORE1_SRAM_PDN_LSB (1U << 8) /* 4b */ 1187 #define VPU_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1188 #define VPU_CORE1_SRAM_SLPB_LSB (1U << 16) /* 4b */ 1189 #define VPU_CORE1_SRAM_SLPB_ACK_LSB (1U << 28) /* 4b */ 1190 /* CAM_PWR_CON (0x10006000+0x344) */ 1191 #define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */ 1192 #define CAM_PWR_ISO_LSB (1U << 1) /* 1b */ 1193 #define CAM_PWR_ON_LSB (1U << 2) /* 1b */ 1194 #define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1195 #define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1196 #define CAM_SRAM_PDN_LSB (1U << 8) /* 4b */ 1197 #define CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1198 /* MFG_2D_PWR_CON (0x10006000+0x348) */ 1199 #define MFG_2D_PWR_RST_B_LSB (1U << 0) /* 1b */ 1200 #define MFG_2D_PWR_ISO_LSB (1U << 1) /* 1b */ 1201 #define MFG_2D_PWR_ON_LSB (1U << 2) /* 1b */ 1202 #define MFG_2D_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1203 #define MFG_2D_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1204 #define MFG_2D_SRAM_PDN_LSB (1U << 8) /* 4b */ 1205 #define MFG_2D_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1206 /* MFG_CORE0_PWR_CON (0x10006000+0x34C) */ 1207 #define MFG_CORE0_PWR_RST_B_LSB (1U << 0) /* 1b */ 1208 #define MFG_CORE0_PWR_ISO_LSB (1U << 1) /* 1b */ 1209 #define MFG_CORE0_PWR_ON_LSB (1U << 2) /* 1b */ 1210 #define MFG_CORE0_PWR_ON_2ND_LSB (1U << 3) /* 1b */ 1211 #define MFG_CORE0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */ 1212 #define MFG_CORE0_SRAM_PDN_LSB (1U << 8) /* 4b */ 1213 #define MFG_CORE0_SRAM_PDN_ACK_LSB (1U << 12) /* 4b */ 1214 /* SYSRAM_CON (0x10006000+0x350) */ 1215 #define IFR_SRAMROM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1216 #define IFR_SRAMROM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1217 #define IFR_SRAMROM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ 1218 #define IFR_SRAMROM_SRAM_PDN_LSB (1U << 16) /* 8b */ 1219 /* SYSROM_CON (0x10006000+0x354) */ 1220 #define IFR_SRAMROM_ROM_PDN_LSB (1U << 0) /* 6b */ 1221 /* SSPM_SRAM_CON (0x10006000+0x358) */ 1222 #define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1223 #define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1224 #define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1225 #define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */ 1226 /* SCP_SRAM_CON (0x10006000+0x35C) */ 1227 #define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1228 #define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1229 #define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */ 1230 #define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */ 1231 /* UFS_SRAM_CON (0x10006000+0x36C) */ 1232 #define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1233 #define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1234 #define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */ 1235 #define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */ 1236 /* DUMMY_SRAM_CON (0x10006000+0x380) */ 1237 #define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */ 1238 #define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */ 1239 #define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */ 1240 #define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */ 1241 /* MD_EXT_BUCK_ISO_CON (0x10006000+0x390) */ 1242 #define VMODEM_BUCK_ELS_EN_LSB (1U << 0) /* 1b */ 1243 #define VMD_BUCK_ELS_EN_LSB (1U << 1) /* 1b */ 1244 /* MD_SRAM_ISO_CON (0x10006000+0x394) */ 1245 #define MD1_SRAM_ISOINT_B_LSB (1U << 0) /* 1b */ 1246 /* MD_EXTRA_PWR_CON (0x10006000+0x398) */ 1247 #define MD1_PWR_PROT_REQ_STA_LSB (1U << 0) /* 1b */ 1248 #define MD2_PWR_PROT_REQ_STA_LSB (1U << 1) /* 1b */ 1249 /* EXT_BUCK_CON (0x10006000+0x3A0) */ 1250 #define RG_VA09_ON_LSB (1U << 0) /* 1b */ 1251 /* MBIST_EFUSE_REPAIR_ACK_STA (0x10006000+0x3D0) */ 1252 #define MBIST_EFUSE_REPAIR_ACK_STA_LSB (1U << 0) /* 32b */ 1253 /* SPM_DVFS_CON (0x10006000+0x400) */ 1254 #define SPM_DVFS_CON_LSB (1U << 0) /* 4b */ 1255 #define SPM_DVFS_ACK_LSB (1U << 30) /* 2b */ 1256 /* SPM_MDBSI_CON (0x10006000+0x404) */ 1257 #define SPM_MDBSI_CON_LSB (1U << 0) /* 3b */ 1258 /* SPM_MAS_PAUSE_MASK_B (0x10006000+0x408) */ 1259 #define SPM_MAS_PAUSE_MASK_B_LSB (1U << 0) /* 32b */ 1260 /* SPM_MAS_PAUSE2_MASK_B (0x10006000+0x40C) */ 1261 #define SPM_MAS_PAUSE2_MASK_B_LSB (1U << 0) /* 32b */ 1262 /* SPM_BSI_GEN (0x10006000+0x410) */ 1263 #define SPM_BSI_START_LSB (1U << 0) /* 1b */ 1264 /* SPM_BSI_EN_SR (0x10006000+0x414) */ 1265 #define SPM_BSI_EN_SR_LSB (1U << 0) /* 32b */ 1266 /* SPM_BSI_CLK_SR (0x10006000+0x418) */ 1267 #define SPM_BSI_CLK_SR_LSB (1U << 0) /* 32b */ 1268 /* SPM_BSI_D0_SR (0x10006000+0x41C) */ 1269 #define SPM_BSI_D0_SR_LSB (1U << 0) /* 32b */ 1270 /* SPM_BSI_D1_SR (0x10006000+0x420) */ 1271 #define SPM_BSI_D1_SR_LSB (1U << 0) /* 32b */ 1272 /* SPM_BSI_D2_SR (0x10006000+0x424) */ 1273 #define SPM_BSI_D2_SR_LSB (1U << 0) /* 32b */ 1274 /* SPM_AP_SEMA (0x10006000+0x428) */ 1275 #define SPM_AP_SEMA_LSB (1U << 0) /* 1b */ 1276 /* SPM_SPM_SEMA (0x10006000+0x42C) */ 1277 #define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */ 1278 /* AP_MDSRC_REQ (0x10006000+0x430) */ 1279 #define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */ 1280 #define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */ 1281 #define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */ 1282 #define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */ 1283 #define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */ 1284 #define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */ 1285 /* SPM2MD_DVFS_CON (0x10006000+0x438) */ 1286 #define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */ 1287 /* MD2SPM_DVFS_CON (0x10006000+0x43C) */ 1288 #define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */ 1289 /* DRAMC_DPY_CLK_SW_CON_RSV (0x10006000+0x440) */ 1290 #define SPM2DRAMC_SHUFFLE_START_LSB (1U << 0) /* 1b */ 1291 #define SPM2DRAMC_SHUFFLE_SWITCH_LSB (1U << 1) /* 1b */ 1292 #define SPM2DPY_DIV2_SYNC_LSB (1U << 2) /* 1b */ 1293 #define SPM2DPY_1PLL_SWITCH_LSB (1U << 3) /* 1b */ 1294 #define SPM2DPY_TEST_CK_MUX_LSB (1U << 4) /* 1b */ 1295 #define SPM2DPY_ASYNC_MODE_LSB (1U << 5) /* 1b */ 1296 #define SPM2TOP_ASYNC_MODE_LSB (1U << 6) /* 1b */ 1297 /* DPY_LP_CON (0x10006000+0x444) */ 1298 #define SC_DDRPHY_LP_SIGNALS_LSB (1U << 0) /* 3b */ 1299 /* CPU_DVFS_REQ (0x10006000+0x448) */ 1300 #define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */ 1301 /* SPM_PLL_CON (0x10006000+0x44C) */ 1302 #define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */ 1303 #define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */ 1304 #define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */ 1305 #define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */ 1306 #define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */ 1307 #define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */ 1308 #define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */ 1309 #define SC_SSPMK_CK_OFF_LSB (1U << 17) /* 1b */ 1310 /* SPM_EMI_BW_MODE (0x10006000+0x450) */ 1311 #define EMI_BW_MODE_LSB (1U << 0) /* 1b */ 1312 #define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */ 1313 #define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */ 1314 #define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */ 1315 /* AP2MD_PEER_WAKEUP (0x10006000+0x454) */ 1316 #define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */ 1317 /* ULPOSC_CON (0x10006000+0x458) */ 1318 #define ULPOSC_EN_LSB (1U << 0) /* 1b */ 1319 #define ULPOSC_RST_LSB (1U << 1) /* 1b */ 1320 #define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */ 1321 #define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */ 1322 /* SPM2MM_CON (0x10006000+0x45C) */ 1323 #define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */ 1324 #define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */ 1325 #define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */ 1326 #define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */ 1327 #define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */ 1328 #define MM2SPM_FORCE_ULTRA_ACK_LSB (1U << 16) /* 1b */ 1329 #define MM2SPM_DBL_OSTD_ACT_ACK_LSB (1U << 17) /* 1b */ 1330 #define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */ 1331 #define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */ 1332 #define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */ 1333 /* DRAMC_DPY_CLK_SW_CON_SEL (0x10006000+0x460) */ 1334 #define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 0) /* 2b */ 1335 #define SW_EMI_CLK_OFF_SEL_LSB (1U << 2) /* 2b */ 1336 #define SW_DPY_MODE_SW_SEL_LSB (1U << 4) /* 2b */ 1337 #define SW_DMSUS_OFF_SEL_LSB (1U << 6) /* 2b */ 1338 #define SW_MEM_CK_OFF_SEL_LSB (1U << 8) /* 2b */ 1339 #define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 10) /* 2b */ 1340 #define SW_DPY_DLL_EN_SEL_LSB (1U << 12) /* 2b */ 1341 #define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 14) /* 2b */ 1342 #define SW_DPY_VREF_EN_SEL_LSB (1U << 16) /* 2b */ 1343 #define SW_PHYPLL_EN_SEL_LSB (1U << 18) /* 2b */ 1344 #define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 20) /* 2b */ 1345 #define SEPERATE_PHY_PWR_SEL_LSB (1U << 23) /* 1b */ 1346 #define SW_DMDRAMCSHU_ACK_SEL_LSB (1U << 24) /* 2b */ 1347 #define SW_EMI_CLK_OFF_ACK_SEL_LSB (1U << 26) /* 2b */ 1348 #define SW_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 28) /* 2b */ 1349 #define SW_DRAMC_DFS_STA_SEL_LSB (1U << 30) /* 2b */ 1350 /* DRAMC_DPY_CLK_SW_CON (0x10006000+0x464) */ 1351 #define SW_DR_GATE_RETRY_EN_LSB (1U << 0) /* 2b */ 1352 #define SW_EMI_CLK_OFF_LSB (1U << 2) /* 2b */ 1353 #define SW_DPY_MODE_SW_LSB (1U << 4) /* 2b */ 1354 #define SW_DMSUS_OFF_LSB (1U << 6) /* 2b */ 1355 #define SW_MEM_CK_OFF_LSB (1U << 8) /* 2b */ 1356 #define SW_DPY_2ND_DLL_EN_LSB (1U << 10) /* 2b */ 1357 #define SW_DPY_DLL_EN_LSB (1U << 12) /* 2b */ 1358 #define SW_DPY_DLL_CK_EN_LSB (1U << 14) /* 2b */ 1359 #define SW_DPY_VREF_EN_LSB (1U << 16) /* 2b */ 1360 #define SW_PHYPLL_EN_LSB (1U << 18) /* 2b */ 1361 #define SW_DDRPHY_FB_CK_EN_LSB (1U << 20) /* 2b */ 1362 #define SC_DR_SHU_EN_ACK_LSB (1U << 24) /* 2b */ 1363 #define EMI_CLK_OFF_ACK_LSB (1U << 26) /* 2b */ 1364 #define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 28) /* 2b */ 1365 #define SC_DRAMC_DFS_STA_LSB (1U << 30) /* 2b */ 1366 /* SPM_S1_MODE_CH (0x10006000+0x468) */ 1367 #define SPM_S1_MODE_CH_LSB (1U << 0) /* 2b */ 1368 #define S1_EMI_CK_SWITCH_LSB (1U << 8) /* 2b */ 1369 /* EMI_SELF_REFRESH_CH_STA (0x10006000+0x46C) */ 1370 #define EMI_SELF_REFRESH_CH_LSB (1U << 0) /* 2b */ 1371 /* DRAMC_DPY_CLK_SW_CON_SEL2 (0x10006000+0x470) */ 1372 #define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 0) /* 1b */ 1373 #define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 1) /* 1b */ 1374 #define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 2) /* 1b */ 1375 #define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 3) /* 1b */ 1376 #define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 4) /* 1b */ 1377 #define SW_DR_SHU_EN_SEL_LSB (1U << 5) /* 1b */ 1378 #define SW_DR_SHU_LEVEL_SEL_LSB (1U << 6) /* 1b */ 1379 #define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 8) /* 2b */ 1380 #define SW_SHU_RESTORE_SEL_LSB (1U << 10) /* 2b */ 1381 #define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 12) /* 2b */ 1382 #define SW_DPHY_RXDLY_TRACK_EN_SEL_LSB (1U << 14) /* 2b */ 1383 #define SW_TX_TRACKING_DIS_SEL_LSB (1U << 16) /* 2b */ 1384 /* DRAMC_DPY_CLK_SW_CON2 (0x10006000+0x474) */ 1385 #define SW_PHYPLL_SHU_EN_LSB (1U << 0) /* 1b */ 1386 #define SW_PHYPLL2_SHU_EN_LSB (1U << 1) /* 1b */ 1387 #define SW_PHYPLL_MODE_SW_LSB (1U << 2) /* 1b */ 1388 #define SW_PHYPLL2_MODE_SW_LSB (1U << 3) /* 1b */ 1389 #define SW_DR_SHORT_QUEUE_LSB (1U << 4) /* 1b */ 1390 #define SW_DR_SHU_EN_LSB (1U << 5) /* 1b */ 1391 #define SW_DR_SHU_LEVEL_LSB (1U << 6) /* 2b */ 1392 #define SW_DPY_BCLK_ENABLE_LSB (1U << 8) /* 2b */ 1393 #define SW_SHU_RESTORE_LSB (1U << 10) /* 2b */ 1394 #define SW_DPHY_PRECAL_UP_LSB (1U << 12) /* 2b */ 1395 #define SW_DPHY_RXDLY_TRACK_EN_LSB (1U << 14) /* 2b */ 1396 #define SW_TX_TRACKING_DIS_LSB (1U << 16) /* 2b */ 1397 /* DRAMC_DMYRD_CON (0x10006000+0x478) */ 1398 #define DRAMC_DMYRD_EN_CH0_LSB (1U << 0) /* 1b */ 1399 #define DRAMC_DMYRD_INTV_SEL_CH0_LSB (1U << 1) /* 1b */ 1400 #define DRAMC_DMYRD_EN_MOD_SEL_CH0_LSB (1U << 2) /* 1b */ 1401 #define DRAMC_DMYRD_EN_CH1_LSB (1U << 8) /* 1b */ 1402 #define DRAMC_DMYRD_INTV_SEL_CH1_LSB (1U << 9) /* 1b */ 1403 #define DRAMC_DMYRD_EN_MOD_SEL_CH1_LSB (1U << 10) /* 1b */ 1404 /* SPM_DRS_CON (0x10006000+0x47C) */ 1405 #define SPM_DRS_DIS_REQ_CH0_LSB (1U << 0) /* 1b */ 1406 #define SPM_DRS_DIS_REQ_CH1_LSB (1U << 1) /* 1b */ 1407 #define SPM_DRS_DIS_ACK_CH0_LSB (1U << 8) /* 1b */ 1408 #define SPM_DRS_DIS_ACK_CH1_LSB (1U << 9) /* 1b */ 1409 /* SPM_SEMA_M0 (0x10006000+0x480) */ 1410 #define SPM_SEMA_M0_LSB (1U << 0) /* 8b */ 1411 /* SPM_SEMA_M1 (0x10006000+0x484) */ 1412 #define SPM_SEMA_M1_LSB (1U << 0) /* 8b */ 1413 /* SPM_SEMA_M2 (0x10006000+0x488) */ 1414 #define SPM_SEMA_M2_LSB (1U << 0) /* 8b */ 1415 /* SPM_SEMA_M3 (0x10006000+0x48C) */ 1416 #define SPM_SEMA_M3_LSB (1U << 0) /* 8b */ 1417 /* SPM_SEMA_M4 (0x10006000+0x490) */ 1418 #define SPM_SEMA_M4_LSB (1U << 0) /* 8b */ 1419 /* SPM_SEMA_M5 (0x10006000+0x494) */ 1420 #define SPM_SEMA_M5_LSB (1U << 0) /* 8b */ 1421 /* SPM_SEMA_M6 (0x10006000+0x498) */ 1422 #define SPM_SEMA_M6_LSB (1U << 0) /* 8b */ 1423 /* SPM_SEMA_M7 (0x10006000+0x49C) */ 1424 #define SPM_SEMA_M7_LSB (1U << 0) /* 8b */ 1425 /* SPM_MAS_PAUSE_MM_MASK_B (0x10006000+0x4A0) */ 1426 #define SPM_MAS_PAUSE_MM_MASK_B_LSB (1U << 0) /* 16b */ 1427 /* SPM_MAS_PAUSE_MCU_MASK_B (0x10006000+0x4A4) */ 1428 #define SPM_MAS_PAUSE_MCU_MASK_B_LSB (1U << 0) /* 16b */ 1429 /* SRAM_DREQ_ACK (0x10006000+0x4AC) */ 1430 #define SRAM_DREQ_ACK_LSB (1U << 0) /* 16b */ 1431 /* SRAM_DREQ_CON (0x10006000+0x4B0) */ 1432 #define SRAM_DREQ_CON_LSB (1U << 0) /* 16b */ 1433 /* SRAM_DREQ_CON_SET (0x10006000+0x4B4) */ 1434 #define SRAM_DREQ_CON_SET_LSB (1U << 0) /* 16b */ 1435 /* SRAM_DREQ_CON_CLR (0x10006000+0x4B8) */ 1436 #define SRAM_DREQ_CON_CLR_LSB (1U << 0) /* 16b */ 1437 /* SPM2EMI_ENTER_ULPM (0x10006000+0x4BC) */ 1438 #define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */ 1439 /* SPM_SSPM_IRQ (0x10006000+0x4C0) */ 1440 #define SPM_SSPM_IRQ_LSB (1U << 0) /* 1b */ 1441 #define SPM_SSPM_IRQ_SEL_LSB (1U << 4) /* 1b */ 1442 /* SPM2PMCU_INT (0x10006000+0x4C4) */ 1443 #define SPM2PMCU_INT_LSB (1U << 0) /* 4b */ 1444 /* SPM2PMCU_INT_SET (0x10006000+0x4C8) */ 1445 #define SPM2PMCU_INT_SET_LSB (1U << 0) /* 4b */ 1446 /* SPM2PMCU_INT_CLR (0x10006000+0x4CC) */ 1447 #define SPM2PMCU_INT_CLR_LSB (1U << 0) /* 4b */ 1448 /* SPM2PMCU_MAILBOX_0 (0x10006000+0x4D0) */ 1449 #define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */ 1450 /* SPM2PMCU_MAILBOX_1 (0x10006000+0x4D4) */ 1451 #define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */ 1452 /* SPM2PMCU_MAILBOX_2 (0x10006000+0x4D8) */ 1453 #define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */ 1454 /* SPM2PMCU_MAILBOX_3 (0x10006000+0x4DC) */ 1455 #define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */ 1456 /* PMCU2SPM_INT (0x10006000+0x4E0) */ 1457 #define PMCU2SPM_INT_LSB (1U << 0) /* 4b */ 1458 /* PMCU2SPM_INT_SET (0x10006000+0x4E4) */ 1459 #define PMCU2SPM_INT_SET_LSB (1U << 0) /* 4b */ 1460 /* PMCU2SPM_INT_CLR (0x10006000+0x4E8) */ 1461 #define PMCU2SPM_INT_CLR_LSB (1U << 0) /* 4b */ 1462 /* PMCU2SPM_MAILBOX_0 (0x10006000+0x4EC) */ 1463 #define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ 1464 /* PMCU2SPM_MAILBOX_1 (0x10006000+0x4F0) */ 1465 #define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ 1466 /* PMCU2SPM_MAILBOX_2 (0x10006000+0x4F4) */ 1467 #define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ 1468 /* PMCU2SPM_MAILBOX_3 (0x10006000+0x4F8) */ 1469 #define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ 1470 /* PMCU2SPM_CFG (0x10006000+0x4FC) */ 1471 #define PMCU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ 1472 #define SPM_PMCU_MAILBOX_REQ_LSB (1U << 8) /* 1b */ 1473 /* MP0_CPU0_IRQ_MASK (0x10006000+0x500) */ 1474 #define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ 1475 #define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */ 1476 /* MP0_CPU1_IRQ_MASK (0x10006000+0x504) */ 1477 #define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ 1478 #define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */ 1479 /* MP0_CPU2_IRQ_MASK (0x10006000+0x508) */ 1480 #define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ 1481 #define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */ 1482 /* MP0_CPU3_IRQ_MASK (0x10006000+0x50C) */ 1483 #define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ 1484 #define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */ 1485 /* MP1_CPU0_IRQ_MASK (0x10006000+0x510) */ 1486 #define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */ 1487 #define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */ 1488 /* MP1_CPU1_IRQ_MASK (0x10006000+0x514) */ 1489 #define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */ 1490 #define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */ 1491 /* MP1_CPU2_IRQ_MASK (0x10006000+0x518) */ 1492 #define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */ 1493 #define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */ 1494 /* MP1_CPU3_IRQ_MASK (0x10006000+0x51C) */ 1495 #define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */ 1496 #define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */ 1497 /* MP0_CPU0_WFI_EN (0x10006000+0x530) */ 1498 #define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ 1499 /* MP0_CPU1_WFI_EN (0x10006000+0x534) */ 1500 #define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ 1501 /* MP0_CPU2_WFI_EN (0x10006000+0x538) */ 1502 #define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ 1503 /* MP0_CPU3_WFI_EN (0x10006000+0x53C) */ 1504 #define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ 1505 /* MP1_CPU0_WFI_EN (0x10006000+0x540) */ 1506 #define MP1_CPU0_WFI_EN_LSB (1U << 0) /* 1b */ 1507 /* MP1_CPU1_WFI_EN (0x10006000+0x544) */ 1508 #define MP1_CPU1_WFI_EN_LSB (1U << 0) /* 1b */ 1509 /* MP1_CPU2_WFI_EN (0x10006000+0x548) */ 1510 #define MP1_CPU2_WFI_EN_LSB (1U << 0) /* 1b */ 1511 /* MP1_CPU3_WFI_EN (0x10006000+0x54C) */ 1512 #define MP1_CPU3_WFI_EN_LSB (1U << 0) /* 1b */ 1513 /* MP0_L2CFLUSH (0x10006000+0x554) */ 1514 #define MP0_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */ 1515 #define MP0_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */ 1516 /* MP1_L2CFLUSH (0x10006000+0x558) */ 1517 #define MP1_L2CFLUSH_REQ_LSB (1U << 0) /* 1b */ 1518 #define MP1_L2CFLUSH_DONE_LSB (1U << 4) /* 1b */ 1519 /* CPU_PTPOD2_CON (0x10006000+0x560) */ 1520 #define MP0_PTPOD2_FBB_EN_LSB (1U << 0) /* 1b */ 1521 #define MP1_PTPOD2_FBB_EN_LSB (1U << 1) /* 1b */ 1522 #define MP0_PTPOD2_SPARK_EN_LSB (1U << 2) /* 1b */ 1523 #define MP1_PTPOD2_SPARK_EN_LSB (1U << 3) /* 1b */ 1524 #define MP0_PTPOD2_FBB_ACK_LSB (1U << 4) /* 1b */ 1525 #define MP1_PTPOD2_FBB_ACK_LSB (1U << 5) /* 1b */ 1526 /* ROOT_CPUTOP_ADDR (0x10006000+0x570) */ 1527 #define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */ 1528 /* ROOT_CORE_ADDR (0x10006000+0x574) */ 1529 #define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */ 1530 /* CPU_SPARE_CON (0x10006000+0x580) */ 1531 #define CPU_SPARE_CON_LSB (1U << 0) /* 32b */ 1532 /* CPU_SPARE_CON_SET (0x10006000+0x584) */ 1533 #define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */ 1534 /* CPU_SPARE_CON_CLR (0x10006000+0x588) */ 1535 #define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ 1536 /* SPM2SW_MAILBOX_0 (0x10006000+0x5D0) */ 1537 #define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */ 1538 /* SPM2SW_MAILBOX_1 (0x10006000+0x5D4) */ 1539 #define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */ 1540 /* SPM2SW_MAILBOX_2 (0x10006000+0x5D8) */ 1541 #define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */ 1542 /* SPM2SW_MAILBOX_3 (0x10006000+0x5DC) */ 1543 #define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */ 1544 /* SW2SPM_INT (0x10006000+0x5E0) */ 1545 #define SW2SPM_INT_LSB (1U << 0) /* 4b */ 1546 /* SW2SPM_INT_SET (0x10006000+0x5E4) */ 1547 #define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */ 1548 /* SW2SPM_INT_CLR (0x10006000+0x5E8) */ 1549 #define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */ 1550 /* SW2SPM_MAILBOX_0 (0x10006000+0x5EC) */ 1551 #define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */ 1552 /* SW2SPM_MAILBOX_1 (0x10006000+0x5F0) */ 1553 #define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */ 1554 /* SW2SPM_MAILBOX_2 (0x10006000+0x5F4) */ 1555 #define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */ 1556 /* SW2SPM_MAILBOX_3 (0x10006000+0x5F8) */ 1557 #define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */ 1558 /* SW2SPM_CFG (0x10006000+0x5FC) */ 1559 #define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */ 1560 #define SPM_SW_MAILBOX_REQ_LSB (1U << 8) /* 1b */ 1561 /* SPM_SW_FLAG (0x10006000+0x600) */ 1562 #define SPM_SW_FLAG_LSB (1U << 0) /* 32b */ 1563 /* SPM_SW_DEBUG (0x10006000+0x604) */ 1564 #define SPM_SW_DEBUG_LSB (1U << 0) /* 32b */ 1565 /* SPM_SW_RSV_0 (0x10006000+0x608) */ 1566 #define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */ 1567 /* SPM_SW_RSV_1 (0x10006000+0x60C) */ 1568 #define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */ 1569 /* SPM_SW_RSV_2 (0x10006000+0x610) */ 1570 #define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */ 1571 /* SPM_SW_RSV_3 (0x10006000+0x614) */ 1572 #define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */ 1573 /* SPM_SW_RSV_4 (0x10006000+0x618) */ 1574 #define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */ 1575 /* SPM_SW_RSV_5 (0x10006000+0x61C) */ 1576 #define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */ 1577 /* SPM_RSV_CON (0x10006000+0x620) */ 1578 #define SPM_RSV_CON_LSB (1U << 0) /* 16b */ 1579 /* SPM_RSV_STA (0x10006000+0x624) */ 1580 #define SPM_RSV_STA_LSB (1U << 0) /* 16b */ 1581 /* SPM_RSV_CON1 (0x10006000+0x628) */ 1582 #define SPM_RSV_CON1_LSB (1U << 0) /* 16b */ 1583 /* SPM_RSV_STA1 (0x10006000+0x62C) */ 1584 #define SPM_RSV_STA1_LSB (1U << 0) /* 16b */ 1585 /* SPM_PASR_DPD_0 (0x10006000+0x630) */ 1586 #define SPM_PASR_DPD_0_LSB (1U << 0) /* 32b */ 1587 /* SPM_PASR_DPD_1 (0x10006000+0x634) */ 1588 #define SPM_PASR_DPD_1_LSB (1U << 0) /* 32b */ 1589 /* SPM_PASR_DPD_2 (0x10006000+0x638) */ 1590 #define SPM_PASR_DPD_2_LSB (1U << 0) /* 32b */ 1591 /* SPM_PASR_DPD_3 (0x10006000+0x63C) */ 1592 #define SPM_PASR_DPD_3_LSB (1U << 0) /* 32b */ 1593 /* SPM_SPARE_CON (0x10006000+0x640) */ 1594 #define SPM_SPARE_CON_LSB (1U << 0) /* 32b */ 1595 /* SPM_SPARE_CON_SET (0x10006000+0x644) */ 1596 #define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */ 1597 /* SPM_SPARE_CON_CLR (0x10006000+0x648) */ 1598 #define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */ 1599 /* SPM_SW_RSV_6 (0x10006000+0x64C) */ 1600 #define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */ 1601 /* SPM_SW_RSV_7 (0x10006000+0x650) */ 1602 #define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */ 1603 /* SPM_SW_RSV_8 (0x10006000+0x654) */ 1604 #define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */ 1605 /* SPM_SW_RSV_9 (0x10006000+0x658) */ 1606 #define SPM_SW_RSV_9_LSB (1U << 0) /* 32b */ 1607 /* SPM_SW_RSV_10 (0x10006000+0x65C) */ 1608 #define SPM_SW_RSV_10_LSB (1U << 0) /* 32b */ 1609 /* SPM_SW_RSV_18 (0x10006000+0x67C) */ 1610 #define SPM_SW_RSV_18_LSB (1U << 0) /* 32b */ 1611 /* SPM_SW_RSV_19 (0x10006000+0x680) */ 1612 #define SPM_SW_RSV_19_LSB (1U << 0) /* 32b */ 1613 /* DVFSRC_EVENT_MASK_CON (0x10006000+0x690) */ 1614 #define DVFSRC_EVENT_MASK_B_LSB (1U << 0) /* 16b */ 1615 #define DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 16) /* 1b */ 1616 /* DVFSRC_EVENT_FORCE_ON (0x10006000+0x694) */ 1617 #define DVFSRC_EVENT_FORCE_ON_LSB (1U << 0) /* 16b */ 1618 #define DVFSRC_EVENT_TRIGGER_FORCE_ON_LSB (1U << 16) /* 1b */ 1619 /* DVFSRC_EVENT_SEL (0x10006000+0x698) */ 1620 #define DVFSRC_EVENT_SEL_LSB (1U << 0) /* 16b */ 1621 /* SPM_DVFS_EVENT_STA (0x10006000+0x69C) */ 1622 #define SPM_DVFS_EVENT_STA_LSB (1U << 0) /* 32b */ 1623 /* SPM_DVFS_EVENT_STA1 (0x10006000+0x6A0) */ 1624 #define SPM_DVFS_EVENT_STA1_LSB (1U << 0) /* 32b */ 1625 /* SPM_DVFS_LEVEL (0x10006000+0x6A4) */ 1626 #define SPM_DVFS_LEVEL_LSB (1U << 0) /* 16b */ 1627 /* DVFS_ABORT_STA (0x10006000+0x6A8) */ 1628 #define RC2SPM_EVENT_ABORT_D2T_LSB (1U << 0) /* 16b */ 1629 #define RC2SPM_EVENT_ABORT_MASK_OR_LSB (1U << 16) /* 1b */ 1630 /* DVFS_ABORT_OTHERS_MASK (0x10006000+0x6AC) */ 1631 #define DVFS_ABORT_OTHERS_MASK_B_LSB (1U << 0) /* 16b */ 1632 /* SPM_DFS_LEVEL (0x10006000+0x6B0) */ 1633 #define SPM_DFS_LEVEL_LSB (1U << 0) /* 4b */ 1634 /* SPM_DVS_LEVEL (0x10006000+0x6B4) */ 1635 #define SPM_VCORE_LEVEL_LSB (1U << 0) /* 8b */ 1636 #define SPM_VSRAM_LEVEL_LSB (1U << 8) /* 8b */ 1637 #define SPM_VMODEM_LEVEL_LSB (1U << 16) /* 8b */ 1638 /* SPM_DVFS_MISC (0x10006000+0x6B8) */ 1639 #define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */ 1640 #define MSDC_DVFS_LEVEL_LSB (1U << 1) /* 4b */ 1641 #define SDIO_READY_TO_SPM_LSB (1U << 7) /* 1b */ 1642 #define MD2AP_CENTRAL_BUCK_GEAR_REQ_D2T_LSB (1U << 8) /* 1b */ 1643 #define MD2AP_CENTRAL_BUCK_GEAR_RDY_D2T_LSB (1U << 9) /* 1b */ 1644 /* SPARE_SRC_REQ_MASK (0x10006000+0x6C0) */ 1645 #define SPARE1_DDREN_MASK_B_LSB (1U << 0) /* 1b */ 1646 #define SPARE1_APSRC_REQ_MASK_B_LSB (1U << 1) /* 1b */ 1647 #define SPARE1_VRF18_REQ_MASK_B_LSB (1U << 2) /* 1b */ 1648 #define SPARE1_INFRA_REQ_MASK_B_LSB (1U << 3) /* 1b */ 1649 #define SPARE1_SRCCLKENA_MASK_B_LSB (1U << 4) /* 1b */ 1650 #define SPARE1_DDREN_2_MASK_B_LSB (1U << 5) /* 1b */ 1651 #define SPARE2_DDREN_MASK_B_LSB (1U << 8) /* 1b */ 1652 #define SPARE2_APSRC_REQ_MASK_B_LSB (1U << 9) /* 1b */ 1653 #define SPARE2_VRF18_REQ_MASK_B_LSB (1U << 10) /* 1b */ 1654 #define SPARE2_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */ 1655 #define SPARE2_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */ 1656 #define SPARE2_DDREN_2_MASK_B_LSB (1U << 13) /* 1b */ 1657 /* SCP_VCORE_LEVEL (0x10006000+0x6C4) */ 1658 #define SCP_VCORE_LEVEL_LSB (1U << 0) /* 8b */ 1659 /* SC_MM_CK_SEL_CON (0x10006000+0x6C8) */ 1660 #define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */ 1661 #define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */ 1662 /* SPARE_ACK_STA (0x10006000+0x6F0) */ 1663 #define SPARE_ACK_SYNC_LSB (1U << 0) /* 32b */ 1664 /* SPARE_ACK_MASK (0x10006000+0x6F4) */ 1665 #define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */ 1666 /* SPM_DVFS_CON1 (0x10006000+0x700) */ 1667 #define SPM_DVFS_CON1_LSB (1U << 0) /* 32b */ 1668 /* SPM_DVFS_CON1_STA (0x10006000+0x704) */ 1669 #define SPM_DVFS_CON1_STA_LSB (1U << 0) /* 32b */ 1670 /* SPM_DVFS_CMD0 (0x10006000+0x710) */ 1671 #define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */ 1672 /* SPM_DVFS_CMD1 (0x10006000+0x714) */ 1673 #define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */ 1674 /* SPM_DVFS_CMD2 (0x10006000+0x718) */ 1675 #define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */ 1676 /* SPM_DVFS_CMD3 (0x10006000+0x71C) */ 1677 #define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */ 1678 /* SPM_DVFS_CMD4 (0x10006000+0x720) */ 1679 #define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */ 1680 /* SPM_DVFS_CMD5 (0x10006000+0x724) */ 1681 #define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */ 1682 /* SPM_DVFS_CMD6 (0x10006000+0x728) */ 1683 #define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */ 1684 /* SPM_DVFS_CMD7 (0x10006000+0x72C) */ 1685 #define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */ 1686 /* SPM_DVFS_CMD8 (0x10006000+0x730) */ 1687 #define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */ 1688 /* SPM_DVFS_CMD9 (0x10006000+0x734) */ 1689 #define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */ 1690 /* SPM_DVFS_CMD10 (0x10006000+0x738) */ 1691 #define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */ 1692 /* SPM_DVFS_CMD11 (0x10006000+0x73C) */ 1693 #define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */ 1694 /* SPM_DVFS_CMD12 (0x10006000+0x740) */ 1695 #define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */ 1696 /* SPM_DVFS_CMD13 (0x10006000+0x744) */ 1697 #define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */ 1698 /* SPM_DVFS_CMD14 (0x10006000+0x748) */ 1699 #define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */ 1700 /* SPM_DVFS_CMD15 (0x10006000+0x74C) */ 1701 #define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */ 1702 /* WDT_LATCH_SPARE0_FIX (0x10006000+0x780) */ 1703 #define WDT_LATCH_SPARE0_FIX_LSB (1U << 0) /* 32b */ 1704 /* WDT_LATCH_SPARE1_FIX (0x10006000+0x784) */ 1705 #define WDT_LATCH_SPARE1_FIX_LSB (1U << 0) /* 32b */ 1706 /* WDT_LATCH_SPARE2_FIX (0x10006000+0x788) */ 1707 #define WDT_LATCH_SPARE2_FIX_LSB (1U << 0) /* 32b */ 1708 /* WDT_LATCH_SPARE3_FIX (0x10006000+0x78C) */ 1709 #define WDT_LATCH_SPARE3_FIX_LSB (1U << 0) /* 32b */ 1710 /* SPARE_ACK_IN_FIX (0x10006000+0x790) */ 1711 #define SPARE_ACK_IN_FIX_LSB (1U << 0) /* 32b */ 1712 /* DCHA_LATCH_RSV0_FIX (0x10006000+0x794) */ 1713 #define DCHA_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */ 1714 /* DCHB_LATCH_RSV0_FIX (0x10006000+0x798) */ 1715 #define DCHB_LATCH_RSV0_FIX_LSB (1U << 0) /* 32b */ 1716 /* PCM_WDT_LATCH_0 (0x10006000+0x800) */ 1717 #define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */ 1718 /* PCM_WDT_LATCH_1 (0x10006000+0x804) */ 1719 #define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */ 1720 /* PCM_WDT_LATCH_2 (0x10006000+0x808) */ 1721 #define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */ 1722 /* PCM_WDT_LATCH_3 (0x10006000+0x80C) */ 1723 #define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */ 1724 /* PCM_WDT_LATCH_4 (0x10006000+0x810) */ 1725 #define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */ 1726 /* PCM_WDT_LATCH_5 (0x10006000+0x814) */ 1727 #define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */ 1728 /* PCM_WDT_LATCH_6 (0x10006000+0x818) */ 1729 #define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */ 1730 /* PCM_WDT_LATCH_7 (0x10006000+0x81C) */ 1731 #define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */ 1732 /* PCM_WDT_LATCH_8 (0x10006000+0x820) */ 1733 #define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */ 1734 /* PCM_WDT_LATCH_9 (0x10006000+0x824) */ 1735 #define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */ 1736 /* WDT_LATCH_SPARE0 (0x10006000+0x828) */ 1737 #define WDT_LATCH_SPARE0_LSB (1U << 0) /* 32b */ 1738 /* WDT_LATCH_SPARE1 (0x10006000+0x82C) */ 1739 #define WDT_LATCH_SPARE1_LSB (1U << 0) /* 32b */ 1740 /* WDT_LATCH_SPARE2 (0x10006000+0x830) */ 1741 #define WDT_LATCH_SPARE2_LSB (1U << 0) /* 32b */ 1742 /* WDT_LATCH_SPARE3 (0x10006000+0x834) */ 1743 #define WDT_LATCH_SPARE3_LSB (1U << 0) /* 32b */ 1744 /* PCM_WDT_LATCH_10 (0x10006000+0x838) */ 1745 #define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */ 1746 /* PCM_WDT_LATCH_11 (0x10006000+0x83C) */ 1747 #define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */ 1748 /* DCHA_GATING_LATCH_0 (0x10006000+0x840) */ 1749 #define DCHA_GATING_LATCH_0_LSB (1U << 0) /* 32b */ 1750 /* DCHA_GATING_LATCH_1 (0x10006000+0x844) */ 1751 #define DCHA_GATING_LATCH_1_LSB (1U << 0) /* 32b */ 1752 /* DCHA_GATING_LATCH_2 (0x10006000+0x848) */ 1753 #define DCHA_GATING_LATCH_2_LSB (1U << 0) /* 32b */ 1754 /* DCHA_GATING_LATCH_3 (0x10006000+0x84C) */ 1755 #define DCHA_GATING_LATCH_3_LSB (1U << 0) /* 32b */ 1756 /* DCHA_GATING_LATCH_4 (0x10006000+0x850) */ 1757 #define DCHA_GATING_LATCH_4_LSB (1U << 0) /* 32b */ 1758 /* DCHA_GATING_LATCH_5 (0x10006000+0x854) */ 1759 #define DCHA_GATING_LATCH_5_LSB (1U << 0) /* 32b */ 1760 /* DCHA_GATING_LATCH_6 (0x10006000+0x858) */ 1761 #define DCHA_GATING_LATCH_6_LSB (1U << 0) /* 32b */ 1762 /* DCHA_GATING_LATCH_7 (0x10006000+0x85C) */ 1763 #define DCHA_GATING_LATCH_7_LSB (1U << 0) /* 32b */ 1764 /* DCHB_GATING_LATCH_0 (0x10006000+0x860) */ 1765 #define DCHB_GATING_LATCH_0_LSB (1U << 0) /* 32b */ 1766 /* DCHB_GATING_LATCH_1 (0x10006000+0x864) */ 1767 #define DCHB_GATING_LATCH_1_LSB (1U << 0) /* 32b */ 1768 /* DCHB_GATING_LATCH_2 (0x10006000+0x868) */ 1769 #define DCHB_GATING_LATCH_2_LSB (1U << 0) /* 32b */ 1770 /* DCHB_GATING_LATCH_3 (0x10006000+0x86C) */ 1771 #define DCHB_GATING_LATCH_3_LSB (1U << 0) /* 32b */ 1772 /* DCHB_GATING_LATCH_4 (0x10006000+0x870) */ 1773 #define DCHB_GATING_LATCH_4_LSB (1U << 0) /* 32b */ 1774 /* DCHB_GATING_LATCH_5 (0x10006000+0x874) */ 1775 #define DCHB_GATING_LATCH_5_LSB (1U << 0) /* 32b */ 1776 /* DCHB_GATING_LATCH_6 (0x10006000+0x878) */ 1777 #define DCHB_GATING_LATCH_6_LSB (1U << 0) /* 32b */ 1778 /* DCHB_GATING_LATCH_7 (0x10006000+0x87C) */ 1779 #define DCHB_GATING_LATCH_7_LSB (1U << 0) /* 32b */ 1780 /* DCHA_LATCH_RSV0 (0x10006000+0x880) */ 1781 #define DCHA_LATCH_RSV0_LSB (1U << 0) /* 32b */ 1782 /* DCHB_LATCH_RSV0 (0x10006000+0x884) */ 1783 #define DCHB_LATCH_RSV0_LSB (1U << 0) /* 32b */ 1784 /* PCM_WDT_LATCH_12 (0x10006000+0x888) */ 1785 #define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */ 1786 /* PCM_WDT_LATCH_13 (0x10006000+0x88C) */ 1787 #define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */ 1788 /* SPM_PC_TRACE_CON (0x10006000+0x8C0) */ 1789 #define SPM_PC_TRACE_OFFSET_LSB (1U << 0) /* 12b */ 1790 #define SPM_PC_TRACE_HW_EN_LSB (1U << 16) /* 1b */ 1791 #define SPM_PC_TRACE_SW_LSB (1U << 17) /* 1b */ 1792 /* SPM_PC_TRACE_G0 (0x10006000+0x8C4) */ 1793 #define SPM_PC_TRACE0_LSB (1U << 0) /* 12b */ 1794 #define SPM_PC_TRACE1_LSB (1U << 16) /* 12b */ 1795 /* SPM_PC_TRACE_G1 (0x10006000+0x8C8) */ 1796 #define SPM_PC_TRACE2_LSB (1U << 0) /* 12b */ 1797 #define SPM_PC_TRACE3_LSB (1U << 16) /* 12b */ 1798 /* SPM_PC_TRACE_G2 (0x10006000+0x8CC) */ 1799 #define SPM_PC_TRACE4_LSB (1U << 0) /* 12b */ 1800 #define SPM_PC_TRACE5_LSB (1U << 16) /* 12b */ 1801 /* SPM_PC_TRACE_G3 (0x10006000+0x8D0) */ 1802 #define SPM_PC_TRACE6_LSB (1U << 0) /* 12b */ 1803 #define SPM_PC_TRACE7_LSB (1U << 16) /* 12b */ 1804 /* SPM_PC_TRACE_G4 (0x10006000+0x8D4) */ 1805 #define SPM_PC_TRACE8_LSB (1U << 0) /* 12b */ 1806 #define SPM_PC_TRACE9_LSB (1U << 16) /* 12b */ 1807 /* SPM_PC_TRACE_G5 (0x10006000+0x8D8) */ 1808 #define SPM_PC_TRACE10_LSB (1U << 0) /* 12b */ 1809 #define SPM_PC_TRACE11_LSB (1U << 16) /* 12b */ 1810 /* SPM_PC_TRACE_G6 (0x10006000+0x8DC) */ 1811 #define SPM_PC_TRACE12_LSB (1U << 0) /* 12b */ 1812 #define SPM_PC_TRACE13_LSB (1U << 16) /* 12b */ 1813 /* SPM_PC_TRACE_G7 (0x10006000+0x8E0) */ 1814 #define SPM_PC_TRACE14_LSB (1U << 0) /* 12b */ 1815 #define SPM_PC_TRACE15_LSB (1U << 16) /* 12b */ 1816 /* SPM_ACK_CHK_CON (0x10006000+0x900) */ 1817 #define SPM_ACK_CHK_SW_EN_LSB (1U << 0) /* 1b */ 1818 #define SPM_ACK_CHK_CLR_ALL_LSB (1U << 1) /* 1b */ 1819 #define SPM_ACK_CHK_CLR_TIMER_LSB (1U << 2) /* 1b */ 1820 #define SPM_ACK_CHK_CLR_IRQ_LSB (1U << 3) /* 1b */ 1821 #define SPM_ACK_CHK_STA_EN_LSB (1U << 4) /* 1b */ 1822 #define SPM_ACK_CHK_WAKEUP_EN_LSB (1U << 5) /* 1b */ 1823 #define SPM_ACK_CHK_WDT_EN_LSB (1U << 6) /* 1b */ 1824 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN_LSB (1U << 7) /* 1b */ 1825 #define SPM_ACK_CHK_HW_EN_LSB (1U << 8) /* 1b */ 1826 #define SPM_ACK_CHK_HW_MODE_LSB (1U << 9) /* 3b */ 1827 #define SPM_ACK_CHK_FAIL_LSB (1U << 15) /* 1b */ 1828 #define SPM_ACK_CHK_SWINT_EN_LSB (1U << 16) /* 16b */ 1829 /* SPM_ACK_CHK_PC (0x10006000+0x904) */ 1830 #define SPM_ACK_CHK_HW_TRIG_PC_VAL_LSB (1U << 0) /* 16b */ 1831 #define SPM_ACK_CHK_HW_TARG_PC_VAL_LSB (1U << 16) /* 16b */ 1832 /* SPM_ACK_CHK_SEL (0x10006000+0x908) */ 1833 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_LSB (1U << 0) /* 5b */ 1834 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_LSB (1U << 5) /* 3b */ 1835 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_LSB (1U << 16) /* 5b */ 1836 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_LSB (1U << 21) /* 3b */ 1837 /* SPM_ACK_CHK_TIMER (0x10006000+0x90C) */ 1838 #define SPM_ACK_CHK_TIMER_VAL_LSB (1U << 0) /* 16b */ 1839 #define SPM_ACK_CHK_TIMER_LSB (1U << 16) /* 16b */ 1840 /* SPM_ACK_CHK_STA (0x10006000+0x910) */ 1841 #define SPM_ACK_CHK_STA_LSB (1U << 0) /* 32b */ 1842 /* SPM_ACK_CHK_LATCH (0x10006000+0x914) */ 1843 #define SPM_ACK_CHK_LATCH_LSB (1U << 0) /* 32b */ 1844 /* SPM_ACK_CHK_CON2 (0x10006000+0x920) */ 1845 #define SPM_ACK_CHK_SW_EN2_LSB (1U << 0) /* 1b */ 1846 #define SPM_ACK_CHK_CLR_ALL2_LSB (1U << 1) /* 1b */ 1847 #define SPM_ACK_CHK_CLR_TIMER2_LSB (1U << 2) /* 1b */ 1848 #define SPM_ACK_CHK_CLR_IRQ2_LSB (1U << 3) /* 1b */ 1849 #define SPM_ACK_CHK_STA_EN2_LSB (1U << 4) /* 1b */ 1850 #define SPM_ACK_CHK_WAKEUP_EN2_LSB (1U << 5) /* 1b */ 1851 #define SPM_ACK_CHK_WDT_EN2_LSB (1U << 6) /* 1b */ 1852 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN2_LSB (1U << 7) /* 1b */ 1853 #define SPM_ACK_CHK_HW_EN2_LSB (1U << 8) /* 1b */ 1854 #define SPM_ACK_CHK_HW_MODE2_LSB (1U << 9) /* 3b */ 1855 #define SPM_ACK_CHK_FAIL2_LSB (1U << 15) /* 1b */ 1856 #define SPM_ACK_CHK_SWINT_EN2_LSB (1U << 16) /* 16b */ 1857 /* SPM_ACK_CHK_PC2 (0x10006000+0x924) */ 1858 #define SPM_ACK_CHK_HW_TRIG_PC_VAL2_LSB (1U << 0) /* 16b */ 1859 #define SPM_ACK_CHK_HW_TARG_PC_VAL2_LSB (1U << 16) /* 16b */ 1860 /* SPM_ACK_CHK_SEL2 (0x10006000+0x928) */ 1861 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL2_LSB (1U << 0) /* 5b */ 1862 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL2_LSB (1U << 5) /* 3b */ 1863 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL2_LSB (1U << 16) /* 5b */ 1864 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL2_LSB (1U << 21) /* 3b */ 1865 /* SPM_ACK_CHK_TIMER2 (0x10006000+0x92C) */ 1866 #define SPM_ACK_CHK_TIMER_VAL2_LSB (1U << 0) /* 16b */ 1867 #define SPM_ACK_CHK_TIMER2_LSB (1U << 16) /* 16b */ 1868 /* SPM_ACK_CHK_STA2 (0x10006000+0x930) */ 1869 #define SPM_ACK_CHK_STA2_LSB (1U << 0) /* 32b */ 1870 /* SPM_ACK_CHK_LATCH2 (0x10006000+0x934) */ 1871 #define SPM_ACK_CHK_LATCH2_LSB (1U << 0) /* 32b */ 1872 /* SPM_ACK_CHK_CON3 (0x10006000+0x940) */ 1873 #define SPM_ACK_CHK_SW_EN3_LSB (1U << 0) /* 1b */ 1874 #define SPM_ACK_CHK_CLR_ALL3_LSB (1U << 1) /* 1b */ 1875 #define SPM_ACK_CHK_CLR_TIMER3_LSB (1U << 2) /* 1b */ 1876 #define SPM_ACK_CHK_CLR_IRQ3_LSB (1U << 3) /* 1b */ 1877 #define SPM_ACK_CHK_STA_EN3_LSB (1U << 4) /* 1b */ 1878 #define SPM_ACK_CHK_WAKEUP_EN3_LSB (1U << 5) /* 1b */ 1879 #define SPM_ACK_CHK_WDT_EN3_LSB (1U << 6) /* 1b */ 1880 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN3_LSB (1U << 7) /* 1b */ 1881 #define SPM_ACK_CHK_HW_EN3_LSB (1U << 8) /* 1b */ 1882 #define SPM_ACK_CHK_HW_MODE3_LSB (1U << 9) /* 3b */ 1883 #define SPM_ACK_CHK_FAIL3_LSB (1U << 15) /* 1b */ 1884 #define SPM_ACK_CHK_SWINT_EN3_LSB (1U << 16) /* 16b */ 1885 /* SPM_ACK_CHK_PC3 (0x10006000+0x944) */ 1886 #define SPM_ACK_CHK_HW_TRIG_PC_VAL3_LSB (1U << 0) /* 16b */ 1887 #define SPM_ACK_CHK_HW_TARG_PC_VAL3_LSB (1U << 16) /* 16b */ 1888 /* SPM_ACK_CHK_SEL3 (0x10006000+0x948) */ 1889 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL3_LSB (1U << 0) /* 5b */ 1890 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL3_LSB (1U << 5) /* 3b */ 1891 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL3_LSB (1U << 16) /* 5b */ 1892 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL3_LSB (1U << 21) /* 3b */ 1893 /* SPM_ACK_CHK_TIMER3 (0x10006000+0x94C) */ 1894 #define SPM_ACK_CHK_TIMER_VAL3_LSB (1U << 0) /* 16b */ 1895 #define SPM_ACK_CHK_TIMER3_LSB (1U << 16) /* 16b */ 1896 /* SPM_ACK_CHK_STA3 (0x10006000+0x950) */ 1897 #define SPM_ACK_CHK_STA3_LSB (1U << 0) /* 32b */ 1898 /* SPM_ACK_CHK_LATCH3 (0x10006000+0x954) */ 1899 #define SPM_ACK_CHK_LATCH3_LSB (1U << 0) /* 32b */ 1900 /* SPM_ACK_CHK_CON4 (0x10006000+0x960) */ 1901 #define SPM_ACK_CHK_SW_EN4_LSB (1U << 0) /* 1b */ 1902 #define SPM_ACK_CHK_CLR_ALL4_LSB (1U << 1) /* 1b */ 1903 #define SPM_ACK_CHK_CLR_TIMER4_LSB (1U << 2) /* 1b */ 1904 #define SPM_ACK_CHK_CLR_IRQ4_LSB (1U << 3) /* 1b */ 1905 #define SPM_ACK_CHK_STA_EN4_LSB (1U << 4) /* 1b */ 1906 #define SPM_ACK_CHK_WAKEUP_EN4_LSB (1U << 5) /* 1b */ 1907 #define SPM_ACK_CHK_WDT_EN4_LSB (1U << 6) /* 1b */ 1908 #define SPM_ACK_CHK_LOCK_PC_TRACE_EN4_LSB (1U << 7) /* 1b */ 1909 #define SPM_ACK_CHK_HW_EN4_LSB (1U << 8) /* 1b */ 1910 #define SPM_ACK_CHK_HW_MODE4_LSB (1U << 9) /* 3b */ 1911 #define SPM_ACK_CHK_FAIL4_LSB (1U << 15) /* 1b */ 1912 #define SPM_ACK_CHK_SWINT_EN4_LSB (1U << 16) /* 16b */ 1913 /* SPM_ACK_CHK_PC4 (0x10006000+0x964) */ 1914 #define SPM_ACK_CHK_HW_TRIG_PC_VAL4_LSB (1U << 0) /* 16b */ 1915 #define SPM_ACK_CHK_HW_TARG_PC_VAL4_LSB (1U << 16) /* 16b */ 1916 /* SPM_ACK_CHK_SEL4 (0x10006000+0x968) */ 1917 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL4_LSB (1U << 0) /* 5b */ 1918 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL4_LSB (1U << 5) /* 3b */ 1919 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL4_LSB (1U << 16) /* 5b */ 1920 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL4_LSB (1U << 21) /* 3b */ 1921 /* SPM_ACK_CHK_TIMER4 (0x10006000+0x96C) */ 1922 #define SPM_ACK_CHK_TIMER_VAL4_LSB (1U << 0) /* 16b */ 1923 #define SPM_ACK_CHK_TIMER4_LSB (1U << 16) /* 16b */ 1924 /* SPM_ACK_CHK_STA4 (0x10006000+0x970) */ 1925 #define SPM_ACK_CHK_STA4_LSB (1U << 0) /* 32b */ 1926 /* SPM_ACK_CHK_LATCH4 (0x10006000+0x974) */ 1927 #define SPM_ACK_CHK_LATCH4_LSB (1U << 0) /* 32b */ 1928 1929 /* --- SPM Flag Define --- */ 1930 #define SPM_FLAG_DIS_CPU_PDN (1U << 0) 1931 #define SPM_FLAG_DIS_INFRA_PDN (1U << 1) 1932 #define SPM_FLAG_DIS_DDRPHY_PDN (1U << 2) 1933 #define SPM_FLAG_DIS_VCORE_DVS (1U << 3) 1934 #define SPM_FLAG_DIS_VCORE_DFS (1U << 4) 1935 #define SPM_FLAG_DIS_COMMON_SCENARIO (1U << 5) 1936 #define SPM_FLAG_DIS_BUS_CLOCK_OFF (1U << 6) 1937 #define SPM_FLAG_DIS_ATF_ABORT (1U << 7) 1938 #define SPM_FLAG_KEEP_CSYSPWRUPACK_HIGH (1U << 8) 1939 #define SPM_FLAG_DIS_VPROC_VSRAM_DVS (1U << 9) 1940 #define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10) 1941 #define SPM_FLAG_EN_MET_DEBUG_USAGE (1U << 11) 1942 #define SPM_FLAG_SODI_CG_MODE (1U << 12) 1943 #define SPM_FLAG_SODI_NO_EVENT (1U << 13) 1944 #define SPM_FLAG_ENABLE_SODI3 (1U << 14) 1945 #define SPM_FLAG_DISABLE_MMSYS_DVFS (1U << 15) 1946 #define SPM_FLAG_DIS_SYSRAM_SLEEP (1U << 16) 1947 #define SPM_FLAG_DIS_SSPM_SRAM_SLEEP (1U << 17) 1948 #define SPM_FLAG_DIS_VMODEM_DVS (1U << 18) 1949 #define SPM_FLAG_SUSPEND_OPTION (1U << 19) 1950 #define SPM_FLAG_DEEPIDLE_OPTION (1U << 20) 1951 #define SPM_FLAG_SODI_OPTION (1U << 21) 1952 #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT22 (1U << 22) 1953 #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT23 (1U << 23) 1954 #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT24 (1U << 24) 1955 #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT25 (1U << 25) 1956 #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT26 (1U << 26) 1957 #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT27 (1U << 27) 1958 #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT28 (1U << 28) 1959 #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT29 (1U << 29) 1960 #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT30 (1U << 30) 1961 #define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT31 (1U << 31) 1962 1963 /* --- SPM Flag1 Define --- */ 1964 #define SPM_FLAG1_RESERVED_BIT0 (1U << 0) 1965 #define SPM_FLAG1_ENABLE_CPU_DORMANT (1U << 1) 1966 #define SPM_FLAG1_ENABLE_CPU_SLEEP_VOLT (1U << 2) 1967 #define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 3) 1968 #define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 4) 1969 #define SPM_FLAG1_VCORE_LP_0P7V (1U << 5) 1970 #define SPM_FLAG1_DISABLE_MCDSR (1U << 6) 1971 #define SPM_FLAG1_DISABLE_NO_RESUME (1U << 7) 1972 #define SPM_FLAG1_BIG_BUCK_OFF_ENABLE (1U << 8) 1973 #define SPM_FLAG1_BIG_BUCK_ON_ENABLE (1U << 9) 1974 #define SPM_FLAG1_RESERVED_BIT10 (1U << 10) 1975 #define SPM_FLAG1_RESERVED_BIT11 (1U << 11) 1976 #define SPM_FLAG1_RESERVED_BIT12 (1U << 12) 1977 #define SPM_FLAG1_RESERVED_BIT13 (1U << 13) 1978 #define SPM_FLAG1_RESERVED_BIT14 (1U << 14) 1979 #define SPM_FLAG1_DIS_ARMPLL_OFF (1U << 15) 1980 #define SPM_FLAG1_DIS_AXI_BUS_TO_26M (1U << 16) 1981 #define SPM_FLAG1_DIS_IMP_DIS (1U << 17) 1982 #define SPM_FLAG1_DIS_IMP_COPY (1U << 18) 1983 #define SPM_FLAG1_DIS_EMI_TOGGLE_WORKAROUND (1U << 19) 1984 #define SPM_FLAG1_DIS_DRAM_ENTER_SREF (1U << 20) 1985 #define SPM_FLAG1_DIS_DRAM_DLL_OFF (1U << 21) 1986 #define SPM_FLAG1_DIS_PHYPLL_OFF (1U << 22) 1987 #define SPM_FLAG1_DIS_MPLL_OFF (1U << 23) 1988 #define SPM_FLAG1_DIS_SYSPLL_OFF (1U << 24) 1989 #define SPM_FLAG1_DIS_TOP_AXI_CLK_OFF (1U << 25) 1990 #define SPM_FLAG1_DIS_PCM_26M_SWITCH (1U << 26) 1991 #define SPM_FLAG1_DIS_CKSQ_OFF (1U << 27) 1992 #define SPM_FLAG1_DIS_SRCVOLTEN_OFF (1U << 28) 1993 #define SPM_FLAG1_DIS_CHB_CG_FREE_EN (1U << 29) 1994 #define SPM_FLAG1_DIS_CHA_DCM_RES (1U << 30) 1995 #define SPM_FLAG1_DIS_SW_MR4 (1U << 31) 1996 1997 /* --- SPM DEBUG Define --- */ 1998 #define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0) 1999 #define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1) 2000 #define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2) 2001 #define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3) 2002 #define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4) 2003 #define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5) 2004 #define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6) 2005 #define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7) 2006 #define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8) 2007 #define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9) 2008 #define SPM_DBG_DEBUG_IDX_NFC_CKBUF_ON (1U << 10) 2009 #define SPM_DBG_DEBUG_IDX_NFC_CKBUF_OFF (1U << 11) 2010 #define SPM_DBG_DEBUG_IDX_CPU_PDN (1U << 12) 2011 #define SPM_DBG_DEBUG_IDX_DPD (1U << 13) 2012 #define SPM_DBG_DEBUG_IDX_CONN_CKBUF_ON (1U << 14) 2013 #define SPM_DBG_DEBUG_IDX_CONN_CKBUF_OFF (1U << 15) 2014 #define SPM_DBG_DEBUG_IDX_VCORE_DVFS_START (1U << 16) 2015 #define SPM_DBG_DEBUG_IDX_DDREN2_WAKE (1U << 17) 2016 #define SPM_DBG_DEBUG_IDX_DDREN2_SLEEP (1U << 18) 2017 #define SPM_DBG_DEBUG_IDX_SSPM_WFI (1U << 19) 2018 #define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 20) 2019 #define SPM_DBG_RESERVED_BIT21 (1U << 21) 2020 #define SPM_DBG_RESERVED_BIT22 (1U << 22) 2021 #define SPM_DBG_RESERVED_BIT23 (1U << 23) 2022 #define SPM_DBG_RESERVED_BIT24 (1U << 24) 2023 #define SPM_DBG_RESERVED_BIT25 (1U << 25) 2024 #define SPM_DBG_RESERVED_BIT26 (1U << 26) 2025 #define SPM_DBG_SODI1_FLAG (1U << 27) 2026 #define SPM_DBG_SODI3_FLAG (1U << 28) 2027 #define SPM_DBG_VCORE_DVFS_FLAG (1U << 29) 2028 #define SPM_DBG_DEEPIDLE_FLAG (1U << 30) 2029 #define SPM_DBG_SUSPEND_FLAG (1U << 31) 2030 2031 /* --- SPM DEBUG1 Define --- */ 2032 #define SPM_DBG1_DRAM_SREF_ACK_TO (1U << 0) 2033 #define SPM_DBG1_PWRAP_SLEEP_ACK_TO (1U << 1) 2034 #define SPM_DBG1_PWRAP_SPI_ACK_TO (1U << 2) 2035 #define SPM_DBG1_DRAM_GATE_ERR_DDREN_WAKEUP (1U << 3) 2036 #define SPM_DBG1_DRAM_GATE_ERR_LEAVE_LP_SCN (1U << 4) 2037 #define SPM_DBG1_RESERVED_BIT5 (1U << 5) 2038 #define SPM_DBG1_RESERVED_BIT6 (1U << 6) 2039 #define SPM_DBG1_RESERVED_BIT7 (1U << 7) 2040 #define SPM_DBG1_RESERVED_BIT8 (1U << 8) 2041 #define SPM_DBG1_RESERVED_BIT9 (1U << 9) 2042 #define SPM_DBG1_RESERVED_BIT10 (1U << 10) 2043 #define SPM_DBG1_RESERVED_BIT11 (1U << 11) 2044 #define SPM_DBG1_RESERVED_BIT12 (1U << 12) 2045 #define SPM_DBG1_RESERVED_BIT13 (1U << 13) 2046 #define SPM_DBG1_RESERVED_BIT14 (1U << 14) 2047 #define SPM_DBG1_RESERVED_BIT15 (1U << 15) 2048 #define SPM_DBG1_RESERVED_BIT16 (1U << 16) 2049 #define SPM_DBG1_RESERVED_BIT17 (1U << 17) 2050 #define SPM_DBG1_RESERVED_BIT18 (1U << 18) 2051 #define SPM_DBG1_RESERVED_BIT19 (1U << 19) 2052 #define SPM_DBG1_RESERVED_BIT20 (1U << 20) 2053 #define SPM_DBG1_RESERVED_BIT21 (1U << 21) 2054 #define SPM_DBG1_RESERVED_BIT22 (1U << 22) 2055 #define SPM_DBG1_RESERVED_BIT23 (1U << 23) 2056 #define SPM_DBG1_RESERVED_BIT24 (1U << 24) 2057 #define SPM_DBG1_RESERVED_BIT25 (1U << 25) 2058 #define SPM_DBG1_RESERVED_BIT26 (1U << 26) 2059 #define SPM_DBG1_RESERVED_BIT27 (1U << 27) 2060 #define SPM_DBG1_RESERVED_BIT28 (1U << 28) 2061 #define SPM_DBG1_RESERVED_BIT29 (1U << 29) 2062 #define SPM_DBG1_RESERVED_BIT30 (1U << 30) 2063 #define SPM_DBG1_RESERVED_BIT31 (1U << 31) 2064 2065 /* --- R0 Define --- */ 2066 #define R0_SC_26M_CK_OFF (1U << 0) 2067 #define R0_BIT1 (1U << 1) 2068 #define R0_SC_MEM_CK_OFF (1U << 2) 2069 #define R0_SC_AXI_CK_OFF (1U << 3) 2070 #define R0_SC_DR_GATE_RETRY_EN_PCM (1U << 4) 2071 #define R0_SC_MD26M_CK_OFF (1U << 5) 2072 #define R0_SC_DPY_MODE_SW_PCM (1U << 6) 2073 #define R0_SC_DMSUS_OFF_PCM (1U << 7) 2074 #define R0_SC_DPY_2ND_DLL_EN_PCM (1U << 8) 2075 #define R0_BIT9 (1U << 9) 2076 #define R0_SC_MPLLOUT_OFF (1U << 10) 2077 #define R0_SC_TX_TRACKING_DIS (1U << 11) 2078 #define R0_SC_DPY_DLL_EN_PCM (1U << 12) 2079 #define R0_SC_DPY_DLL_CK_EN_PCM (1U << 13) 2080 #define R0_SC_DPY_VREF_EN_PCM (1U << 14) 2081 #define R0_SC_PHYPLL_EN_PCM (1U << 15) 2082 #define R0_SC_DDRPHY_FB_CK_EN_PCM (1U << 16) 2083 #define R0_SC_DPY_BCLK_ENABLE (1U << 17) 2084 #define R0_SC_MPLL_OFF (1U << 18) 2085 #define R0_SC_SHU_RESTORE (1U << 19) 2086 #define R0_SC_CKSQ0_OFF (1U << 20) 2087 #define R0_SC_CKSQ1_OFF (1U << 21) 2088 #define R0_SC_DR_SHU_EN_PCM (1U << 22) 2089 #define R0_SC_DPHY_PRECAL_UP (1U << 23) 2090 #define R0_SC_MPLL_S_OFF (1U << 24) 2091 #define R0_SC_DPHY_RXDLY_TRACK_EN (1U << 25) 2092 #define R0_SC_PHYPLL_SHU_EN_PCM (1U << 26) 2093 #define R0_SC_PHYPLL2_SHU_EN_PCM (1U << 27) 2094 #define R0_SC_PHYPLL_MODE_SW_PCM (1U << 28) 2095 #define R0_SC_PHYPLL2_MODE_SW_PCM (1U << 29) 2096 #define R0_SC_DR_SHU_LEVEL_PCM0 (1U << 30) 2097 #define R0_SC_DR_SHU_LEVEL_PCM1 (1U << 31) 2098 2099 /* --- R7 Define --- */ 2100 #define R7_PWRAP_SLEEP_REQ (1U << 0) 2101 #define R7_EMI_CLK_OFF_REQ (1U << 1) 2102 #define R7_TOP_MAS_PAU_REQ (1U << 2) 2103 #define R7_SPM2CKSYS_MEM_CK_MUX_UPDATE (1U << 3) 2104 #define R7_PCM_CK_SEL0 (1U << 4) 2105 #define R7_PCM_CK_SEL1 (1U << 5) 2106 #define R7_SPM2RC_DVS_DONE (1U << 6) 2107 #define R7_FREQH_PAUSE_MPLL (1U << 7) 2108 #define R7_SC_26M_CK_SEL (1U << 8) 2109 #define R7_PCM_TIMER_SET (1U << 9) 2110 #define R7_PCM_TIMER_CLR (1U << 10) 2111 #define R7_SRCVOLTEN (1U << 11) 2112 #define R7_CSYSPWRUPACK (1U << 12) 2113 #define R7_IM_SLEEP_ENABLE (1U << 13) 2114 #define R7_SRCCLKENO_0 (1U << 14) 2115 #define R7_SYSRST (1U << 15) 2116 #define R7_MD_APSRC_ACK (1U << 16) 2117 #define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17) 2118 #define R7_SC_AXI_DCM_DIS (1U << 18) 2119 #define R7_FREQH_PAUSE_MAIN (1U << 19) 2120 #define R7_FREQH_PAUSE_MEM (1U << 20) 2121 #define R7_SRCCLKENO_1 (1U << 21) 2122 #define R7_WDT_KICK_P (1U << 22) 2123 #define R7_SPM2RC_EVENT_ABORT_ACK (1U << 23) 2124 #define R7_WAKEUP_EXT_W_SEL (1U << 24) 2125 #define R7_WAKEUP_EXT_R_SEL (1U << 25) 2126 #define R7_PMIC_IRQ_REQ_EN (1U << 26) 2127 #define R7_FORCE_26M_WAKE (1U << 27) 2128 #define R7_FORCE_APSRC_WAKE (1U << 28) 2129 #define R7_FORCE_INFRA_WAKE (1U << 29) 2130 #define R7_FORCE_VRF18_WAKE (1U << 30) 2131 #define R7_SC_DR_SHORT_QUEUE_PCM (1U << 31) 2132 2133 /* --- R12 Define --- */ 2134 #define R12_PCM_TIMER (1U << 0) 2135 #define R12_SSPM_WDT_EVENT_B (1U << 1) 2136 #define R12_KP_IRQ_B (1U << 2) 2137 #define R12_APWDT_EVENT_B (1U << 3) 2138 #define R12_APXGPT1_EVENT_B (1U << 4) 2139 #define R12_CONN2AP_SPM_WAKEUP_B (1U << 5) 2140 #define R12_EINT_EVENT_B (1U << 6) 2141 #define R12_CONN_WDT_IRQ_B (1U << 7) 2142 #define R12_CCIF0_EVENT_B (1U << 8) 2143 #define R12_LOWBATTERY_IRQ_B (1U << 9) 2144 #define R12_SSPM_SPM_IRQ_B (1U << 10) 2145 #define R12_SCP_SPM_IRQ_B (1U << 11) 2146 #define R12_SCP_WDT_EVENT_B (1U << 12) 2147 #define R12_PCM_WDT_WAKEUP_B (1U << 13) 2148 #define R12_USB_CDSC_B (1U << 14) 2149 #define R12_USB_POWERDWN_B (1U << 15) 2150 #define R12_SYS_TIMER_EVENT_B (1U << 16) 2151 #define R12_EINT_EVENT_SECURE_B (1U << 17) 2152 #define R12_CCIF1_EVENT_B (1U << 18) 2153 #define R12_UART0_IRQ_B (1U << 19) 2154 #define R12_AFE_IRQ_MCU_B (1U << 20) 2155 #define R12_THERM_CTRL_EVENT_B (1U << 21) 2156 #define R12_SYS_CIRQ_IRQ_B (1U << 22) 2157 #define R12_MD2AP_PEER_EVENT_B (1U << 23) 2158 #define R12_CSYSPWREQ_B (1U << 24) 2159 #define R12_MD1_WDT_B (1U << 25) 2160 #define R12_CLDMA_EVENT_B (1U << 26) 2161 #define R12_SEJ_WDT_GPT_B (1U << 27) 2162 #define R12_ALL_SSPM_WAKEUP_B (1U << 28) 2163 #define R12_CPU_IRQ_B (1U << 29) 2164 #define R12_CPU_WFI_AND_B (1U << 30) 2165 #define R12_MCUSYS_IDLE_TO_EMI_ALL_B (1U << 31) 2166 2167 /* --- R12ext Define --- */ 2168 #define R12EXT_26M_WAKE (1U << 0) 2169 #define R12EXT_26M_SLEEP (1U << 1) 2170 #define R12EXT_INFRA_WAKE (1U << 2) 2171 #define R12EXT_INFRA_SLEEP (1U << 3) 2172 #define R12EXT_APSRC_WAKE (1U << 4) 2173 #define R12EXT_APSRC_SLEEP (1U << 5) 2174 #define R12EXT_VRF18_WAKE (1U << 6) 2175 #define R12EXT_VRF18_SLEEP (1U << 7) 2176 #define R12EXT_DVFS_ALL_STATE (1U << 8) 2177 #define R12EXT_DVFS_LEVEL_STATE0 (1U << 9) 2178 #define R12EXT_DVFS_LEVEL_STATE1 (1U << 10) 2179 #define R12EXT_DVFS_LEVEL_STATE2 (1U << 11) 2180 #define R12EXT_DDREN_WAKE (1U << 12) 2181 #define R12EXT_DDREN_SLEEP (1U << 13) 2182 #define R12EXT_NFC_CLK_BUF_WAKE (1U << 14) 2183 #define R12EXT_NFC_CLK_BUF_SLEEP (1U << 15) 2184 #define R12EXT_CONN_CLK_BUF_WAKE (1U << 16) 2185 #define R12EXT_CONN_CLK_BUF_SLEEP (1U << 17) 2186 #define R12EXT_MD_DVFS_ERROR_STATUS (1U << 18) 2187 #define R12EXT_DVFS_LEVEL_STATE3 (1U << 19) 2188 #define R12EXT_DVFS_LEVEL_STATE4 (1U << 20) 2189 #define R12EXT_DVFS_LEVEL_STATE5 (1U << 21) 2190 #define R12EXT_DVFS_LEVEL_STATE6 (1U << 22) 2191 #define R12EXT_DVFS_LEVEL_STATE7 (1U << 23) 2192 #define R12EXT_DVFS_LEVEL_STATE8 (1U << 24) 2193 #define R12EXT_DVFS_LEVEL_STATE9 (1U << 25) 2194 #define R12EXT_DVFS_LEVEL_STATE_G0 (1U << 26) 2195 #define R12EXT_DVFS_LEVEL_STATE_G1 (1U << 27) 2196 #define R12EXT_DVFS_LEVEL_STATE_G2 (1U << 28) 2197 #define R12EXT_DVFS_LEVEL_STATE_G3 (1U << 29) 2198 #define R12EXT_HYBRID_DDREN_SLEEP (1U << 30) 2199 #define R12EXT_HYBRID_DDREN_WAKE (1U << 31) 2200 2201 /* --- R13 Define --- */ 2202 #define R13_EXT_SRCCLKENI_0 (1U << 0) 2203 #define R13_EXT_SRCCLKENI_1 (1U << 1) 2204 #define R13_MD1_SRCCLKENA (1U << 2) 2205 #define R13_MD1_APSRC_REQ (1U << 3) 2206 #define R13_CONN_DDR_EN (1U << 4) 2207 #define R13_MD2_SRCCLKENA (1U << 5) 2208 #define R13_SSPM_SRCCLKENA (1U << 6) 2209 #define R13_SSPM_APSRC_REQ (1U << 7) 2210 #define R13_MD_STATE (1U << 8) 2211 #define R13_EMI_CLK_OFF_2_ACK (1U << 9) 2212 #define R13_MM_STATE (1U << 10) 2213 #define R13_SSPM_STATE (1U << 11) 2214 #define R13_MD_DDR_EN (1U << 12) 2215 #define R13_CONN_STATE (1U << 13) 2216 #define R13_CONN_SRCCLKENA (1U << 14) 2217 #define R13_CONN_APSRC_REQ (1U << 15) 2218 #define R13_SLEEP_EVENT_STA (1U << 16) 2219 #define R13_WAKE_EVENT_STA (1U << 17) 2220 #define R13_EMI_IDLE (1U << 18) 2221 #define R13_CSYSPWRUPREQ (1U << 19) 2222 #define R13_PWRAP_SLEEP_ACK (1U << 20) 2223 #define R13_EMI_CLK_OFF_ACK_ALL (1U << 21) 2224 #define R13_TOP_MAS_PAU_ACK (1U << 22) 2225 #define R13_SW_DMDRAMCSHU_ACK_ALL (1U << 23) 2226 #define R13_RC2SPM_EVENT_ABORT_MASK_OR (1U << 24) 2227 #define R13_DR_SHORT_QUEUE_ACK_ALL (1U << 25) 2228 #define R13_INFRA_AUX_IDLE (1U << 26) 2229 #define R13_DVFS_ALL_STATE (1U << 27) 2230 #define R13_RC2SPM_EVENT_ABORT_OR (1U << 28) 2231 #define R13_DRAMC_SPCMD_APSRC_REQ (1U << 29) 2232 #define R13_MD1_VRF18_REQ (1U << 30) 2233 #define R13_C2K_VRF18_REQ (1U << 31) 2234 2235 #define is_cpu_pdn(flags) (!((flags) & SPM_FLAG_DIS_CPU_PDN)) 2236 #define is_infra_pdn(flags) (!((flags) & SPM_FLAG_DIS_INFRA_PDN)) 2237 #define is_ddrphy_pdn(flags) (!((flags) & SPM_FLAG_DIS_DDRPHY_PDN)) 2238 2239 #define MP0_SPMC_SRAM_DORMANT_EN (1<<0) 2240 #define MP1_SPMC_SRAM_DORMANT_EN (1<<1) 2241 #define MP2_SPMC_SRAM_DORMANT_EN (1<<2) 2242 2243 #define EVENT_VEC(event, resume, imme, pc) \ 2244 (((pc) << 16) | \ 2245 (!!(imme) << 7) | \ 2246 (!!(resume) << 6) | \ 2247 ((event) & 0x3f)) 2248 2249 #define SPM_PROJECT_CODE 0xb16 2250 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) 2251 2252 /************************************** 2253 * Config and Parameter 2254 **************************************/ 2255 #define POWER_ON_VAL1_DEF 0x00015800 2256 #define PCM_FSM_STA_DEF 0x00108490 2257 #define SPM_WAKEUP_EVENT_MASK_DEF 0xF0F92218 2258 #define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ 2259 #define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) 2260 2261 /************************************** 2262 * Define and Declare 2263 **************************************/ 2264 /* PCM_PWR_IO_EN */ 2265 #define PCM_PWRIO_EN_R0 (1U << 0) 2266 #define PCM_PWRIO_EN_R7 (1U << 7) 2267 #define PCM_RF_SYNC_R0 (1U << 16) 2268 #define PCM_RF_SYNC_R6 (1U << 22) 2269 #define PCM_RF_SYNC_R7 (1U << 23) 2270 2271 /* SPM_SWINT */ 2272 #define PCM_SW_INT0 (1U << 0) 2273 #define PCM_SW_INT1 (1U << 1) 2274 #define PCM_SW_INT2 (1U << 2) 2275 #define PCM_SW_INT3 (1U << 3) 2276 #define PCM_SW_INT4 (1U << 4) 2277 #define PCM_SW_INT5 (1U << 5) 2278 #define PCM_SW_INT6 (1U << 6) 2279 #define PCM_SW_INT7 (1U << 7) 2280 #define PCM_SW_INT8 (1U << 8) 2281 #define PCM_SW_INT9 (1U << 9) 2282 #define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ 2283 PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ 2284 PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ 2285 PCM_SW_INT0) 2286 /* SPM_IRQ_MASK */ 2287 #define ISRM_TWAM (1U << 2) 2288 #define ISRM_PCM_RETURN (1U << 3) 2289 #define ISRM_RET_IRQ0 (1U << 8) 2290 #define ISRM_RET_IRQ1 (1U << 9) 2291 #define ISRM_RET_IRQ2 (1U << 10) 2292 #define ISRM_RET_IRQ3 (1U << 11) 2293 #define ISRM_RET_IRQ4 (1U << 12) 2294 #define ISRM_RET_IRQ5 (1U << 13) 2295 #define ISRM_RET_IRQ6 (1U << 14) 2296 #define ISRM_RET_IRQ7 (1U << 15) 2297 #define ISRM_RET_IRQ8 (1U << 16) 2298 #define ISRM_RET_IRQ9 (1U << 17) 2299 #define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | \ 2300 ISRM_RET_IRQ7 | ISRM_RET_IRQ6 | \ 2301 ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \ 2302 ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | \ 2303 ISRM_RET_IRQ1) 2304 #define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) 2305 #define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) 2306 2307 /* SPM_IRQ_STA */ 2308 #define ISRS_TWAM (1U << 2) 2309 #define ISRS_PCM_RETURN (1U << 3) 2310 #define ISRS_SW_INT0 (1U << 4) 2311 #define ISRC_TWAM ISRS_TWAM 2312 #define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN 2313 #define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) 2314 2315 /* SPM_WAKEUP_MISC */ 2316 #define WAKE_MISC_TWAM (1U << 18) 2317 #define WAKE_MISC_PCM_TIMER (1U << 19) 2318 #define WAKE_MISC_CPU_WAKE (1U << 20) 2319 2320 enum SPM_WAKE_SRC_LIST { 2321 WAKE_SRC_R12_PCM_TIMER = (1U << 0), 2322 WAKE_SRC_R12_SSPM_WDT_EVENT_B = (1U << 1), 2323 WAKE_SRC_R12_KP_IRQ_B = (1U << 2), 2324 WAKE_SRC_R12_APWDT_EVENT_B = (1U << 3), 2325 WAKE_SRC_R12_APXGPT1_EVENT_B = (1U << 4), 2326 WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B = (1U << 5), 2327 WAKE_SRC_R12_EINT_EVENT_B = (1U << 6), 2328 WAKE_SRC_R12_CONN_WDT_IRQ_B = (1U << 7), 2329 WAKE_SRC_R12_CCIF0_EVENT_B = (1U << 8), 2330 WAKE_SRC_R12_LOWBATTERY_IRQ_B = (1U << 9), 2331 WAKE_SRC_R12_SSPM_SPM_IRQ_B = (1U << 10), 2332 WAKE_SRC_R12_SCP_SPM_IRQ_B = (1U << 11), 2333 WAKE_SRC_R12_SCP_WDT_EVENT_B = (1U << 12), 2334 WAKE_SRC_R12_PCM_WDT_WAKEUP_B = (1U << 13), 2335 WAKE_SRC_R12_USB_CDSC_B = (1U << 14), 2336 WAKE_SRC_R12_USB_POWERDWN_B = (1U << 15), 2337 WAKE_SRC_R12_SYS_TIMER_EVENT_B = (1U << 16), 2338 WAKE_SRC_R12_EINT_EVENT_SECURE_B = (1U << 17), 2339 WAKE_SRC_R12_CCIF1_EVENT_B = (1U << 18), 2340 WAKE_SRC_R12_UART0_IRQ_B = (1U << 19), 2341 WAKE_SRC_R12_AFE_IRQ_MCU_B = (1U << 20), 2342 WAKE_SRC_R12_THERM_CTRL_EVENT_B = (1U << 21), 2343 WAKE_SRC_R12_SYS_CIRQ_IRQ_B = (1U << 22), 2344 WAKE_SRC_R12_MD2AP_PEER_EVENT_B = (1U << 23), 2345 WAKE_SRC_R12_CSYSPWREQ_B = (1U << 24), 2346 WAKE_SRC_R12_MD1_WDT_B = (1U << 25), 2347 WAKE_SRC_R12_CLDMA_EVENT_B = (1U << 26), 2348 WAKE_SRC_R12_SEJ_WDT_GPT_B = (1U << 27), 2349 WAKE_SRC_R12_ALL_SSPM_WAKEUP_B = (1U << 28), 2350 WAKE_SRC_R12_CPU_IRQ_B = (1U << 29), 2351 WAKE_SRC_R12_CPU_WFI_AND_B = (1U << 30), 2352 }; 2353 2354 struct pcm_desc { 2355 const char *version; 2356 const uint32_t *base; 2357 const uint32_t base_dma; 2358 const uint32_t size; 2359 const uint32_t sess; 2360 const uint32_t replace; 2361 const uint32_t addr_2nd; 2362 const uint32_t reserved; 2363 2364 uint32_t vec0; 2365 uint32_t vec1; 2366 uint32_t vec2; 2367 uint32_t vec3; 2368 uint32_t vec4; 2369 uint32_t vec5; 2370 uint32_t vec6; 2371 uint32_t vec7; 2372 uint32_t vec8; 2373 uint32_t vec9; 2374 uint32_t vec10; 2375 uint32_t vec11; 2376 uint32_t vec12; 2377 uint32_t vec13; 2378 uint32_t vec14; 2379 uint32_t vec15; 2380 }; 2381 2382 struct pwr_ctrl { 2383 uint32_t pcm_flags; 2384 uint32_t pcm_flags1; 2385 uint32_t timer_val; 2386 uint32_t wake_src; 2387 2388 /* SPM_AP_STANDBY_CON */ 2389 uint8_t wfi_op; 2390 uint8_t mp0_cputop_idle_mask; 2391 uint8_t mp1_cputop_idle_mask; 2392 uint8_t mcusys_idle_mask; 2393 uint8_t mm_mask_b; 2394 uint8_t md_ddr_en_0_dbc_en; 2395 uint8_t md_ddr_en_1_dbc_en; 2396 uint8_t md_mask_b; 2397 uint8_t sspm_mask_b; 2398 uint8_t scp_mask_b; 2399 uint8_t srcclkeni_mask_b; 2400 uint8_t md_apsrc_1_sel; 2401 uint8_t md_apsrc_0_sel; 2402 uint8_t conn_ddr_en_dbc_en; 2403 uint8_t conn_mask_b; 2404 uint8_t conn_apsrc_sel; 2405 2406 /* SPM_SRC_REQ */ 2407 uint8_t spm_apsrc_req; 2408 uint8_t spm_f26m_req; 2409 uint8_t spm_infra_req; 2410 uint8_t spm_vrf18_req; 2411 uint8_t spm_ddren_req; 2412 uint8_t spm_rsv_src_req; 2413 uint8_t spm_ddren_2_req; 2414 uint8_t cpu_md_dvfs_sop_force_on; 2415 2416 /* SPM_SRC_MASK */ 2417 uint8_t csyspwreq_mask; 2418 uint8_t ccif0_md_event_mask_b; 2419 uint8_t ccif0_ap_event_mask_b; 2420 uint8_t ccif1_md_event_mask_b; 2421 uint8_t ccif1_ap_event_mask_b; 2422 uint8_t ccif2_md_event_mask_b; 2423 uint8_t ccif2_ap_event_mask_b; 2424 uint8_t ccif3_md_event_mask_b; 2425 uint8_t ccif3_ap_event_mask_b; 2426 uint8_t md_srcclkena_0_infra_mask_b; 2427 uint8_t md_srcclkena_1_infra_mask_b; 2428 uint8_t conn_srcclkena_infra_mask_b; 2429 uint8_t ufs_infra_req_mask_b; 2430 uint8_t srcclkeni_infra_mask_b; 2431 uint8_t md_apsrc_req_0_infra_mask_b; 2432 uint8_t md_apsrc_req_1_infra_mask_b; 2433 uint8_t conn_apsrcreq_infra_mask_b; 2434 uint8_t ufs_srcclkena_mask_b; 2435 uint8_t md_vrf18_req_0_mask_b; 2436 uint8_t md_vrf18_req_1_mask_b; 2437 uint8_t ufs_vrf18_req_mask_b; 2438 uint8_t gce_vrf18_req_mask_b; 2439 uint8_t conn_infra_req_mask_b; 2440 uint8_t gce_apsrc_req_mask_b; 2441 uint8_t disp0_apsrc_req_mask_b; 2442 uint8_t disp1_apsrc_req_mask_b; 2443 uint8_t mfg_req_mask_b; 2444 uint8_t vdec_req_mask_b; 2445 2446 /* SPM_SRC2_MASK */ 2447 uint8_t md_ddr_en_0_mask_b; 2448 uint8_t md_ddr_en_1_mask_b; 2449 uint8_t conn_ddr_en_mask_b; 2450 uint8_t ddren_sspm_apsrc_req_mask_b; 2451 uint8_t ddren_scp_apsrc_req_mask_b; 2452 uint8_t disp0_ddren_mask_b; 2453 uint8_t disp1_ddren_mask_b; 2454 uint8_t gce_ddren_mask_b; 2455 uint8_t ddren_emi_self_refresh_ch0_mask_b; 2456 uint8_t ddren_emi_self_refresh_ch1_mask_b; 2457 2458 /* SPM_WAKEUP_EVENT_MASK */ 2459 uint32_t spm_wakeup_event_mask; 2460 2461 /* SPM_WAKEUP_EVENT_EXT_MASK */ 2462 uint32_t spm_wakeup_event_ext_mask; 2463 2464 /* SPM_SRC3_MASK */ 2465 uint8_t md_ddr_en_2_0_mask_b; 2466 uint8_t md_ddr_en_2_1_mask_b; 2467 uint8_t conn_ddr_en_2_mask_b; 2468 uint8_t ddren2_sspm_apsrc_req_mask_b; 2469 uint8_t ddren2_scp_apsrc_req_mask_b; 2470 uint8_t disp0_ddren2_mask_b; 2471 uint8_t disp1_ddren2_mask_b; 2472 uint8_t gce_ddren2_mask_b; 2473 uint8_t ddren2_emi_self_refresh_ch0_mask_b; 2474 uint8_t ddren2_emi_self_refresh_ch1_mask_b; 2475 2476 uint8_t mp0_cpu0_wfi_en; 2477 uint8_t mp0_cpu1_wfi_en; 2478 uint8_t mp0_cpu2_wfi_en; 2479 uint8_t mp0_cpu3_wfi_en; 2480 2481 uint8_t mp1_cpu0_wfi_en; 2482 uint8_t mp1_cpu1_wfi_en; 2483 uint8_t mp1_cpu2_wfi_en; 2484 uint8_t mp1_cpu3_wfi_en; 2485 }; 2486 2487 struct wake_status { 2488 uint32_t assert_pc; 2489 uint32_t r12; 2490 uint32_t r12_ext; 2491 uint32_t raw_sta; 2492 uint32_t raw_ext_sta; 2493 uint32_t wake_misc; 2494 uint32_t timer_out; 2495 uint32_t r13; 2496 uint32_t r15; 2497 uint32_t idle_sta; 2498 uint32_t req_sta; 2499 uint32_t debug_flag; 2500 uint32_t debug_flag1; 2501 uint32_t event_reg; 2502 uint32_t isr; 2503 uint32_t sw_flag; 2504 uint32_t sw_flag1; 2505 uint32_t log_index; 2506 }; 2507 2508 typedef struct spm_data { 2509 unsigned int cmd; 2510 union { 2511 struct { 2512 unsigned int sys_timestamp_l; 2513 unsigned int sys_timestamp_h; 2514 unsigned int sys_src_clk_l; 2515 unsigned int sys_src_clk_h; 2516 unsigned int spm_opt; 2517 } suspend; 2518 struct { 2519 unsigned int args1; 2520 unsigned int args2; 2521 unsigned int args3; 2522 unsigned int args4; 2523 unsigned int args5; 2524 unsigned int args6; 2525 unsigned int args7; 2526 } args; 2527 } u; 2528 } spm_data_t; 2529 2530 enum { 2531 SPM_SUSPEND, 2532 SPM_RESUME 2533 }; 2534 2535 extern void spm_disable_pcm_timer(void); 2536 extern void spm_set_bootaddr(unsigned long bootaddr); 2537 extern void spm_set_cpu_status(int cpu); 2538 extern void spm_set_power_control(const struct pwr_ctrl *pwrctrl); 2539 extern void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); 2540 extern void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl); 2541 extern void spm_send_cpu_wakeup_event(void); 2542 extern void spm_get_wakeup_status(struct wake_status *wakesta); 2543 extern void spm_clean_after_wakeup(void); 2544 extern void spm_output_wake_reason(struct wake_status *wakesta, 2545 const char *scenario); 2546 extern void spm_set_pcm_wdt(int en); 2547 extern void spm_lock_get(void); 2548 extern void spm_lock_release(void); 2549 extern void spm_boot_init(void); 2550 extern const char *spm_get_firmware_version(void); 2551 2552 #endif /* SPM_H */ 2553