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Searched refs:WPR (Results 1 – 25 of 25) sorted by relevance

/external/llvm-project/llvm/tools/llvm-exegesis/lib/
DSchedClassResolution.cpp59 for (const auto *WPR = STI.getWriteProcResBegin(&SCDesc), in getNonRedundantWriteProcRes() local
61 WPR != WPREnd; ++WPR) { in getNonRedundantWriteProcRes()
63 SM.getProcResource(WPR->ProcResourceIdx); in getNonRedundantWriteProcRes()
66 Result.push_back({WPR->ProcResourceIdx, WPR->Cycles}); in getNonRedundantWriteProcRes()
67 ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->Cycles; in getNonRedundantWriteProcRes()
71 float RemainingCycles = WPR->Cycles; in getNonRedundantWriteProcRes()
82 Result.push_back({WPR->ProcResourceIdx, in getNonRedundantWriteProcRes()
182 for (const MCWriteProcResEntry &WPR : WPRS) { in computeIdealizedProcResPressure() local
185 SM.getProcResource(WPR.ProcResourceIdx); in computeIdealizedProcResPressure()
188 DensePressure[WPR.ProcResourceIdx] += WPR.Cycles; in computeIdealizedProcResPressure()
[all …]
DAnalysis.cpp405 for (const auto &WPR : RSC.NonRedundantWriteProcRes) { in printSchedClassDescHtml() local
408 SM.getProcResource(WPR.ProcResourceIdx)->Name); in printSchedClassDescHtml()
409 OS << "</span>: " << WPR.Cycles << "</li>"; in printSchedClassDescHtml()
/external/llvm/lib/Target/
DTargetSubtargetInfo.cpp23 const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, in TargetSubtargetInfo() argument
26 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) { in TargetSubtargetInfo()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetSubtargetInfo.cpp20 const MCWriteProcResEntry *WPR, in TargetSubtargetInfo() argument
23 : MCSubtargetInfo(TT, CPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) { in TargetSubtargetInfo()
/external/llvm-project/llvm/lib/CodeGen/
DTargetSubtargetInfo.cpp20 const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, in TargetSubtargetInfo() argument
23 : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {} in TargetSubtargetInfo()
/external/llvm/lib/MC/
DMCSubtargetInfo.cpp42 const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, in MCSubtargetInfo() argument
46 ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL), in MCSubtargetInfo()
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_rtc.h443 (__HANDLE__)->Instance->WPR = 0xCA; \
444 (__HANDLE__)->Instance->WPR = 0x53; \
454 (__HANDLE__)->Instance->WPR = 0xFF; \
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_rtc.h443 (__HANDLE__)->Instance->WPR = 0xCA; \
444 (__HANDLE__)->Instance->WPR = 0x53; \
454 (__HANDLE__)->Instance->WPR = 0xFF; \
/external/llvm-project/llvm/lib/MC/
DMCSubtargetInfo.cpp225 const MCWriteProcResEntry *WPR, in MCSubtargetInfo() argument
231 ProcFeatures(PF), ProcDesc(PD), WriteProcResTable(WPR), in MCSubtargetInfo()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCSubtargetInfo.cpp212 const MCWriteProcResEntry *WPR, in MCSubtargetInfo() argument
216 WriteProcResTable(WPR), WriteLatencyTable(WL), in MCSubtargetInfo()
/external/llvm/include/llvm/Target/
DTargetSubtargetInfo.h59 const MCWriteProcResEntry *WPR,
/external/llvm/include/llvm/MC/
DMCSubtargetInfo.h58 const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetSubtargetInfo.h67 const MCWriteProcResEntry *WPR,
/external/llvm-project/llvm/include/llvm/CodeGen/
DTargetSubtargetInfo.h64 const MCWriteProcResEntry *WPR,
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCSubtargetInfo.h96 const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
/external/llvm-project/llvm/include/llvm/MC/
DMCSubtargetInfo.h98 const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenSubtargetInfo.inc8086 const MCWriteProcResEntry *WPR,
8091 WPR, WL, RA, IS, OC, FP) { }
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc3766 const MCWriteProcResEntry *WPR,
3771 WPR, WL, RA, IS, OC, FP) { }
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
Dstm32l476xx.h759 …__IO uint32_t WPR; /*!< RTC write protection register, Address… member
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenSubtargetInfo.inc19330 const MCWriteProcResEntry *WPR,
19335 WPR, WL, RA, IS, OC, FP) { }
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenSubtargetInfo.inc23062 const MCWriteProcResEntry *WPR,
23067 WPR, WL, RA, IS, OC, FP) { }
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenSubtargetInfo.inc19151 const MCWriteProcResEntry *WPR,
19156 WPR, WL, RA, IS, OC, FP) { }
/external/toolchain-utils/android_bench_suite/panorama_input/
Dtest_003.ppm2317 ….(#3-(3-(1,)(" ���-&B;3>5-ZQI^WP]VOXSK,'  RLJ�����������������WPR/(*.&'1'&MCBRHFB7…
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart1.csv12734 ,"CL","PVR","Porvenir","Porvenir","MA","--34----","RL","1207","WPR","5318S 07022W",
12735 ,"CL","WPR","Porvenir Apt","Porvenir Apt","MA","--34----","RL","0901",,"5315S 07019W",
D2013-1_UNLOCODE_CodeListPart3.csv26678 ,"US","WPR","Westport","Westport","CT","--3-----","RL","0201",,"4108N 07321W",