| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 3592 void abs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
3595 void add(const ZRegister& zd,
3597 const ZRegister& zn,
3598 const ZRegister& zm);
3601 void add(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
3604 void add(const ZRegister& zd, const ZRegister& zn, int imm8, int shift = -1);
3613 void adr(const ZRegister& zd, const SVEMemOperand& addr);
3622 void and_(const ZRegister& zd,
3624 const ZRegister& zn,
3625 const ZRegister& zm);
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| D | macro-assembler-sve-aarch64.cc | 33 const ZRegister& zd, in AddSubHelper()
34 const ZRegister& zn, in AddSubHelper()
58 ZRegister scratch = temps.AcquireZ().WithLaneSize(zn.GetLaneSizeInBits()); in AddSubHelper()
70 const ZRegister& zd, in TrySingleAddSub()
71 const ZRegister& zn, in TrySingleAddSub()
94 const ZRegister& zd, in IntWideImmHelper()
95 const ZRegister& zn, in IntWideImmHelper()
119 ZRegister scratch = in IntWideImmHelper()
129 void MacroAssembler::Mul(const ZRegister& zd, in Mul()
130 const ZRegister& zn, in Mul()
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| D | assembler-sve-aarch64.cc | 50 void Assembler::adr(const ZRegister& zd, const SVEMemOperand& addr) { in adr()
86 void Assembler::SVELogicalImmediate(const ZRegister& zdn, in SVELogicalImmediate()
100 void Assembler::and_(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in and_()
107 void Assembler::dupm(const ZRegister& zd, uint64_t imm) { in dupm()
115 void Assembler::eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in eor()
122 void Assembler::orr(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in orr()
130 void Assembler::and_(const ZRegister& zd, in and_()
131 const ZRegister& zn, in and_()
132 const ZRegister& zm) { in and_()
139 void Assembler::bic(const ZRegister& zd, in bic()
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| D | macro-assembler-aarch64.h | 543 const ZRegister& dst,
544 const ZRegister& src);
547 const ZRegister& dst,
549 const ZRegister& src);
560 inline bool ShouldGenerateMovprfx(const ZRegister& dst, in ShouldGenerateMovprfx()
561 const ZRegister& src) { in ShouldGenerateMovprfx()
566 inline bool ShouldGenerateMovprfx(const ZRegister& dst, in ShouldGenerateMovprfx()
568 const ZRegister& src) { in ShouldGenerateMovprfx()
3068 void MASM(const ZRegister& zd, \
3070 const ZRegister& zn, \
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| D | registers-aarch64.h | 53 class ZRegister; variable
293 ZRegister Z() const;
590 class ZRegister : public CPURegister {
592 VIXL_DECLARE_REGISTER_COMMON(ZRegister, ZRegister, CPURegister) in VIXL_DECLARE_REGISTER_COMMON() argument
594 explicit ZRegister(int code, int lane_size_in_bits = kUnknownSize) in VIXL_DECLARE_REGISTER_COMMON()
602 ZRegister(int code, VectorFormat format) in ZRegister() function
612 ZRegister VnB() const { return ZRegister(GetCode(), kBRegSize); } in VnB()
613 ZRegister VnH() const { return ZRegister(GetCode(), kHRegSize); } in VnH()
614 ZRegister VnS() const { return ZRegister(GetCode(), kSRegSize); } in VnS()
615 ZRegister VnD() const { return ZRegister(GetCode(), kDRegSize); } in VnD()
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| D | operands-aarch64.h | 477 explicit SVEMemOperand(ZRegister base, uint64_t offset = 0)
523 SVEMemOperand(Register base, ZRegister offset, M mod) in SVEMemOperand()
550 SVEMemOperand(ZRegister base,
551 ZRegister offset,
624 ZRegister GetVectorBase() const { in GetVectorBase()
627 return ZRegister(base_); in GetVectorBase()
635 ZRegister GetVectorOffset() const { in GetVectorOffset()
638 return ZRegister(regoffset_); in GetVectorOffset()
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| D | registers-aarch64.cc | 71 VIXL_STATIC_ASSERT(VRegister::GetMaxCode() == ZRegister::GetMaxCode()); in GetMaxCodeFor()
73 VIXL_ASSERT(VRegister::GetMaxCode() == ZRegister::GetMaxCode()); in GetMaxCodeFor()
135 U(ZRegister, Z, V) \
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| /external/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 225 VIXL_CHECK(ZRegister(7).Is(z7)); in TEST()
290 VIXL_CHECK(ZRegister(0, kBRegSize).Is(z0.VnB())); in TEST()
291 VIXL_CHECK(ZRegister(1, kHRegSize).Is(z1.VnH())); in TEST()
292 VIXL_CHECK(ZRegister(2, kSRegSize).Is(z2.VnS())); in TEST()
293 VIXL_CHECK(ZRegister(3, kDRegSize).Is(z3.VnD())); in TEST()
296 VIXL_CHECK(ZRegister(0, kFormatVnB).Is(z0.VnB())); in TEST()
297 VIXL_CHECK(ZRegister(1, kFormatVnH).Is(z1.VnH())); in TEST()
298 VIXL_CHECK(ZRegister(2, kFormatVnS).Is(z2.VnS())); in TEST()
299 VIXL_CHECK(ZRegister(3, kFormatVnD).Is(z3.VnD())); in TEST()
666 static Variant GetVariant(ZRegister) { return kSVE; } in TEST() argument
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| D | test-assembler-sve-aarch64.cc | 110 const ZRegister& zdn, in InsrHelper()
445 ZRegister zd = z0.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
446 ZRegister za = z1.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
447 ZRegister zn = z2.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
448 ZRegister zm = z3.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
468 ZRegister mla_da_result = z10.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
469 ZRegister mla_dn_result = z11.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
470 ZRegister mla_dm_result = z12.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
471 ZRegister mla_d_result = z13.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
487 ZRegister mls_da_result = z20.WithLaneSize(lane_size_in_bits); in MlaMlsHelper()
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| D | test-utils-aarch64.cc | 358 const ZRegister& reg, in EqualSVELane()
689 DumpRegisters<ZRegister>(masm, dump_base, z_offset); in Dump()
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| D | test-utils-aarch64.h | 395 const ZRegister& reg,
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