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/external/llvm-project/llvm/test/Instrumentation/HeapProfiler/
Dmasked-load-store.ll26 ; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
27 ; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
29 ; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1
30 ; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
32 ; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
33 ; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64
44 ; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
45 ; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
47 ; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 3
48 ; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP3]] to i64
[all …]
/external/llvm-project/llvm/test/Instrumentation/AddressSanitizer/
Dasan-masked-load-store.ll34 ; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
35 ; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
37 ; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1
38 ; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
40 ; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
41 ; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64
52 ; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
53 ; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
55 ; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 3
56 ; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP3]] to i64
[all …]
Dasan-detect-invalid-pointer-pair.ll20 ; CMP: [[P:%[0-9A-Za-z]+]] = ptrtoint i8* %p to i64
21 ; CMP: [[Q:%[0-9A-Za-z]+]] = ptrtoint i8* %q to i64
31 ; SUB: [[P:%[0-9A-Za-z]+]] = ptrtoint i8* %p to i64
32 ; SUB: [[Q:%[0-9A-Za-z]+]] = ptrtoint i8* %q to i64
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/AMDGPU/
Dcttz-ctlz.ll7 ; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
8 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
27 ; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
28 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
29 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTLZ]]
47 ; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
48 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
49 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTLZ]]
67 ; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
[all …]
/external/llvm/test/Transforms/SimplifyCFG/AMDGPU/
Dcttz-ctlz.ll7 ; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
8 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
27 ; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
28 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
29 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTLZ]]
47 ; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
48 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
49 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTLZ]]
67 ; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
[all …]
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll8 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
9 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
27 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
28 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
47 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
48 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
67 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
68 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
87 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
88 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
[all …]
/external/jemalloc_new/
D.gitignore32 /test/integration/[A-Za-z]*
33 !/test/integration/[A-Za-z]*.*
37 /test/integration/cpp/[A-Za-z]*
38 !/test/integration/cpp/[A-Za-z]*.*
44 /test/stress/[A-Za-z]*
45 !/test/stress/[A-Za-z]*.*
49 /test/unit/[A-Za-z]*
50 !/test/unit/[A-Za-z]*.*
/external/llvm/test/Transforms/InstCombine/
Dindexed-gep-compares.ll21 ; CHECK: %[[INDEX:[0-9A-Za-z.]+]] = phi i32 [ %[[ADD:[0-9A-Za-z.]+]], %bb ], [ %Offset, %entry ]
25 ; CHECK: %[[PTR:[0-9A-Za-z.]+]] = getelementptr inbounds i32, i32* %A, i32 %[[INDEX]]
48 ; CHECK: %[[INDEX:[0-9A-Za-z.]+]] = phi i32 [ %[[ADD:[0-9A-Za-z.]+]], %bb ], [ %Offset, %entry ]
52 ; CHECK: %[[TOPTR:[0-9A-Za-z.]+]] = inttoptr i32 %[[ADD:[0-9A-Za-z.]+]] to i32*
53 ; CHECK: %[[PTR:[0-9A-Za-z.]+]] = getelementptr inbounds i32, i32* %[[TOPTR]], i32 %[[INDEX]]
74 ; CHECK-NOT: %cond = icmp sgt i32 %{{[0-9A-Za-z.]+}}, 100
99 ; CHECK: %cond = icmp sgt i32 %{{[0-9A-Za-z.]+}}, 100
127 ; CHECK: %[[INDEX:[0-9A-Za-z.]+]] = phi i32 [ %[[ADD:[0-9A-Za-z.]+]], %bb ], [ %Offset, %cont ]
131 ; CHECK: %[[PTR:[0-9A-Za-z.]+]] = getelementptr inbounds i32, i32* %A, i32 %[[INDEX]]
161 ; CHECK: %[[INDEX:[0-9A-Za-z.]+]] = phi i32 [ %[[ADD:[0-9A-Za-z.]+]], %bb ], [ %Offset, %cont ]
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dindexed-gep-compares.ll21 ; CHECK: %[[INDEX:[0-9A-Za-z.]+]] = phi i32 [ %[[ADD:[0-9A-Za-z.]+]], %bb ], [ %Offset, %entry ]
25 ; CHECK: %[[PTR:[0-9A-Za-z.]+]] = getelementptr inbounds i32, i32* %A, i32 %[[INDEX]]
48 ; CHECK: %[[INDEX:[0-9A-Za-z.]+]] = phi i32 [ %[[ADD:[0-9A-Za-z.]+]], %bb ], [ %Offset, %entry ]
52 ; CHECK: %[[TOPTR:[0-9A-Za-z.]+]] = inttoptr i32 %[[ADD:[0-9A-Za-z.]+]] to i32*
53 ; CHECK: %[[PTR:[0-9A-Za-z.]+]] = getelementptr inbounds i32, i32* %[[TOPTR]], i32 %[[INDEX]]
74 ; CHECK-NOT: %cond = icmp sgt i32 %{{[0-9A-Za-z.]+}}, 100
99 ; CHECK: %cond = icmp sgt i32 %{{[0-9A-Za-z.]+}}, 100
127 ; CHECK: %[[INDEX:[0-9A-Za-z.]+]] = phi i32 [ %[[ADD:[0-9A-Za-z.]+]], %bb ], [ %Offset, %cont ]
131 ; CHECK: %[[PTR:[0-9A-Za-z.]+]] = getelementptr inbounds i32, i32* %A, i32 %[[INDEX]]
161 ; CHECK: %[[INDEX:[0-9A-Za-z.]+]] = phi i32 [ %[[ADD:[0-9A-Za-z.]+]], %bb ], [ %Offset, %cont ]
[all …]
/external/e2fsprogs/tests/
Dfilter.sed1 /^debugfs [1-9]\.[0-9]*[^ ]* ([0-9]*-[A-Za-z]*-[0-9]*)/d
2 /^dumpe2fs [1-9]\.[0-9]*[^ ]* ([0-9]*-[A-Za-z]*-[0-9]*)/d
3 /^e2fsck [1-9]\.[0-9]*[^ ]* ([0-9]*-[A-Za-z]*-[0-9]*)/d
4 /^mke2fs [1-9]\.[0-9]*[^ ]* ([0-9]*-[A-Za-z]*-[0-9]*)/d
5 /^resize2fs [1-9]\.[0-9]*[^ ]* ([0-9]*-[A-Za-z]*-[0-9]*)/d
6 /^tune2fs [1-9]\.[0-9]*[^ ]* ([0-9]*-[A-Za-z]*-[0-9]*)/d
7 /^e2image [1-9]\.[0-9]*[^ ]* ([0-9]*-[A-Za-z]*-[0-9]*)/d
/external/llvm-project/mlir/test/Dialect/SCF/
Dops.mlir83 // CHECK-SAME: %[[ARG0:[A-Za-z0-9]+]]:
84 // CHECK-SAME: %[[ARG1:[A-Za-z0-9]+]]:
85 // CHECK-SAME: %[[ARG2:[A-Za-z0-9]+]]:
86 // CHECK-SAME: %[[ARG3:[A-Za-z0-9]+]]:
87 // CHECK-SAME: %[[ARG4:[A-Za-z0-9]+]]:
125 // CHECK-SAME: %[[ARG0:[A-Za-z0-9]+]]:
126 // CHECK-SAME: %[[ARG1:[A-Za-z0-9]+]]:
127 // CHECK-SAME: %[[ARG2:[A-Za-z0-9]+]]:
148 // CHECK-SAME: %[[ARG0:[A-Za-z0-9]+]]:
149 // CHECK-SAME: %[[ARG1:[A-Za-z0-9]+]]:
[all …]
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/AArch64/
Dcttz-ctlz.ll5 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
6 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
7 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
24 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
25 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
26 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/Mips/
Dcttz-ctlz.ll5 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
6 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
7 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
24 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
25 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
26 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
/external/llvm/test/Transforms/SimplifyCFG/AArch64/
Dcttz-ctlz.ll5 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
6 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
7 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
24 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
25 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
26 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
/external/llvm/test/Transforms/SimplifyCFG/Mips/
Dcttz-ctlz.ll5 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
6 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
7 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
24 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
25 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
26 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
/external/llvm/test/Transforms/SimplifyCFG/ARM/
Dcttz-ctlz.ll5 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
6 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
7 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
24 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
25 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
26 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
/external/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll7 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
8 ; CHECK-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
26 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
27 ; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
28 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll7 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
8 ; CHECK-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
26 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
27 ; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
28 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dtail-dup-layout.ll29 ;CHECK-NEXT: bc 12, 1, .[[OPT1LABEL:[_0-9A-Za-z]+]]
32 ;CHECK-NEXT: bne 0, .[[OPT2LABEL:[_0-9A-Za-z]+]]
33 ;CHECK-NEXT: .[[TEST3LABEL:[_0-9A-Za-z]+]]: # %test3
35 ;CHECK-NEXT: bne 0, .[[OPT3LABEL:[_0-9A-Za-z]+]]
36 ;CHECK-NEXT: .[[TEST4LABEL:[_0-9A-Za-z]+]]: # %test4
38 ;CHECK-NEXT: bne 0, .[[OPT4LABEL:[_0-9A-Za-z]+]]
39 ;CHECK-NEXT: .[[EXITLABEL:[_0-9A-Za-z]+]]: # %exit
120 ;CHECK-NEXT: bc 12, 1, .[[OPT1LABEL:[_0-9A-Za-z]+]]
123 ;CHECK-NEXT: bne 0, .[[OPT2LABEL:[_0-9A-Za-z]+]]
124 ;CHECK-NEXT: .[[TEST3LABEL:[_0-9A-Za-z]+]]: # %test3
[all …]
Dtail-dup-break-cfg.ll16 ;CHECK-NEXT: bc 12, 1, [[BODY1LABEL:[._0-9A-Za-z]+]]
19 ;CHECK-NEXT: bne 0, [[BODY2LABEL:[._0-9A-Za-z]+]]
20 ;CHECK: [[EXITLABEL:[._0-9A-Za-z]+]]: # %exit
25 ;CHECK-NEXT: [[BODY2LABEL:[._0-9A-Za-z]+]]:
58 ;CHECK-NEXT: bc 4, 1, [[TEST2LABEL:[._0-9A-Za-z]+]]
62 ;CHECK-NEXT: beq 0, [[EXITLABEL:[._0-9A-Za-z]+]]
64 ;CHECK: [[EXITLABEL:[._0-9A-Za-z]+]]: # %exit
/external/e2fsprogs/lib/ss/
Dct_c.sed47 s/^unimplemented [A-Za-z_0-9]*/request ss_unimplemented/
117 s/[^A-Za-z_0-9].*//
119 s/[A-Za-z_0-9]*//
135 /^[^A-Za-z_0-9]/ {
140 s/[^A-Za-z_0-9].*//
142 s/[A-Za-z_0-9]*//
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Duniform-cfg.ll7 ; GCN: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]]
35 ; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]]
63 ; GCN: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]]
91 ; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]]
122 ; GCN: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]]
147 ; GCN: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]]
169 ; GCN: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]]
198 ; GCN: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]]
201 ; GCN: s_branch [[ENDIF_LABEL:[0-9_A-Za-z]+]]
253 ; GCN: s_cbranch_scc1 [[EXIT:[A-Za-z0-9_]+]]
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Duniform-cfg.ll7 ; SI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]]
37 ; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]]
64 ; SI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]]
94 ; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]]
124 ; SI: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]]
149 ; SI: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]]
171 ; SI-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]]
200 ; SI-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]]
204 ; SI: s_branch [[ENDIF_LABEL:[0-9_A-Za-z]+]]
255 ; SI: s_cbranch_scc1 [[EXIT:[A-Za-z0-9_]+]]
[all …]
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dfunctionalize-if.mlir26 // CHECK: computation = @[[FUNCTIONALIZE_FUNC:[A-Za-z0-9_]*]]
32 // CHECK-SAME: else_branch = @[[ELSE_FUNC:[A-Za-z0-9_]*]]
33 // CHECK-SAME: then_branch = @[[THEN_FUNC:[A-Za-z0-9_]*]]
/external/llvm-project/mlir/test/Transforms/
Dloop-coalescing.mlir127 // CHECK-SAME: %[[orig_lb1:[A-Za-z0-9]+]]:
128 // CHECK-SAME: %[[orig_ub1:[A-Za-z0-9]+]]:
129 // CHECK-SAME: %[[orig_step1:[A-Za-z0-9]+]]:
130 // CHECK-SAME: %[[orig_lb2:[A-Za-z0-9]+]]:
131 // CHECK-SAME: %[[orig_ub2:[A-Za-z0-9]+]]:
132 // CHECK-SAME: %[[orig_step2:[A-Za-z0-9]+]]:

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