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Searched refs:_reg_PHY_PER_CS_TRAINING_EN (Results 1 – 4 of 4) sorted by relevance

/external/arm-trusted-firmware/drivers/renesas/rcar/ddr/ddr_b/
Dboot_init_dram.c3101 ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); in init_ddr()
3106 _reg_PHY_PER_CS_TRAINING_EN, in init_ddr()
3312 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00); in wdqdm_ana1()
3339 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, in wdqdm_ana1()
3342 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, in wdqdm_ana1()
Dddr_regdef.h212 #define _reg_PHY_PER_CS_TRAINING_EN 0x000000ccU macro
/external/arm-trusted-firmware/drivers/renesas/rzg/ddr/ddr_b/
Dddr_regdef.h214 #define _reg_PHY_PER_CS_TRAINING_EN 0x000000ccU macro
Dboot_init_dram.c2544 _reg_PHY_PER_CS_TRAINING_EN, in init_ddr()
2737 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00); in wdqdm_ana1()
2763 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, in wdqdm_ana1()