/external/llvm-project/llvm/test/CodeGen/RISCV/ |
D | bswap-ctlz-cttz-ctpop.ll | 18 ; RV32I-NEXT: slli a1, a0, 8 21 ; RV32I-NEXT: slli a0, a0, 24 22 ; RV32I-NEXT: or a0, a0, a1 23 ; RV32I-NEXT: srli a0, a0, 16 32 ; RV32I-NEXT: srli a1, a0, 8 36 ; RV32I-NEXT: srli a2, a0, 24 38 ; RV32I-NEXT: slli a2, a0, 8 41 ; RV32I-NEXT: slli a0, a0, 24 42 ; RV32I-NEXT: or a0, a0, a2 43 ; RV32I-NEXT: or a0, a0, a1 [all …]
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D | rv64Zbb.ll | 12 ; RV64I-NEXT: not a0, a0 13 ; RV64I-NEXT: sllw a0, a0, a1 14 ; RV64I-NEXT: not a0, a0 19 ; RV64IB-NEXT: slow a0, a0, a1 24 ; RV64IBB-NEXT: slow a0, a0, a1 35 ; RV64I-NEXT: not a0, a0 36 ; RV64I-NEXT: sll a0, a0, a1 37 ; RV64I-NEXT: not a0, a0 42 ; RV64IB-NEXT: slo a0, a0, a1 47 ; RV64IBB-NEXT: slo a0, a0, a1 [all …]
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D | imm.ll | 16 ; RV32I-NEXT: mv a0, zero 21 ; RV64I-NEXT: mv a0, zero 29 ; RV32I-NEXT: addi a0, zero, 2047 34 ; RV64I-NEXT: addi a0, zero, 2047 42 ; RV32I-NEXT: addi a0, zero, -2048 47 ; RV64I-NEXT: addi a0, zero, -2048 55 ; RV32I-NEXT: lui a0, 423811 56 ; RV32I-NEXT: addi a0, a0, -1297 61 ; RV64I-NEXT: lui a0, 423811 62 ; RV64I-NEXT: addiw a0, a0, -1297 [all …]
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D | rv64Zbbp.ll | 15 ; RV64I-NEXT: and a0, a1, a0 20 ; RV64IB-NEXT: andn a0, a0, a1 25 ; RV64IBB-NEXT: andn a0, a0, a1 30 ; RV64IBP-NEXT: andn a0, a0, a1 41 ; RV64I-NEXT: and a0, a1, a0 46 ; RV64IB-NEXT: andn a0, a0, a1 51 ; RV64IBB-NEXT: andn a0, a0, a1 56 ; RV64IBP-NEXT: andn a0, a0, a1 67 ; RV64I-NEXT: or a0, a1, a0 72 ; RV64IB-NEXT: orn a0, a0, a1 [all …]
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D | setcc-logic.ll | 10 ; RV32I-NEXT: xor a0, a0, a1 12 ; RV32I-NEXT: or a0, a0, a1 13 ; RV32I-NEXT: seqz a0, a0 18 ; RV64I-NEXT: xor a0, a0, a1 20 ; RV64I-NEXT: or a0, a0, a1 21 ; RV64I-NEXT: slli a0, a0, 32 22 ; RV64I-NEXT: srli a0, a0, 32 23 ; RV64I-NEXT: seqz a0, a0 34 ; RV32I-NEXT: xor a0, a0, a1 36 ; RV32I-NEXT: or a0, a0, a1 [all …]
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D | alu8.ll | 14 ; RV32I-NEXT: addi a0, a0, 1 19 ; RV64I-NEXT: addi a0, a0, 1 28 ; RV32I-NEXT: slli a0, a0, 24 29 ; RV32I-NEXT: srai a0, a0, 24 30 ; RV32I-NEXT: slti a0, a0, 2 35 ; RV64I-NEXT: slli a0, a0, 56 36 ; RV64I-NEXT: srai a0, a0, 56 37 ; RV64I-NEXT: slti a0, a0, 2 47 ; RV32I-NEXT: andi a0, a0, 255 48 ; RV32I-NEXT: sltiu a0, a0, 3 [all …]
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D | rv64m-exhaustive-w-insts.ll | 12 ; RV64IM-NEXT: mulw a0, a0, a1 21 ; RV64IM-NEXT: mulw a0, a0, a1 30 ; RV64IM-NEXT: mulw a0, a0, a1 39 ; RV64IM-NEXT: mulw a0, a0, a1 48 ; RV64IM-NEXT: mulw a0, a0, a1 57 ; RV64IM-NEXT: mulw a0, a0, a1 66 ; RV64IM-NEXT: mulw a0, a0, a1 75 ; RV64IM-NEXT: mulw a0, a0, a1 84 ; RV64IM-NEXT: mulw a0, a0, a1 93 ; RV64IM-NEXT: mulw a0, a0, a1 [all …]
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D | sext-zext-trunc.ll | 10 ; RV32I-NEXT: andi a0, a0, 1 11 ; RV32I-NEXT: neg a0, a0 16 ; RV64I-NEXT: andi a0, a0, 1 17 ; RV64I-NEXT: neg a0, a0 26 ; RV32I-NEXT: andi a0, a0, 1 27 ; RV32I-NEXT: neg a0, a0 32 ; RV64I-NEXT: andi a0, a0, 1 33 ; RV64I-NEXT: neg a0, a0 42 ; RV32I-NEXT: andi a0, a0, 1 43 ; RV32I-NEXT: neg a0, a0 [all …]
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D | rv64i-exhaustive-w-insts.ll | 14 ; RV64I-NEXT: addw a0, a0, a1 23 ; RV64I-NEXT: addw a0, a0, a1 32 ; RV64I-NEXT: addw a0, a0, a1 41 ; RV64I-NEXT: addw a0, a0, a1 50 ; RV64I-NEXT: addw a0, a0, a1 59 ; RV64I-NEXT: addw a0, a0, a1 68 ; RV64I-NEXT: addw a0, a0, a1 77 ; RV64I-NEXT: addw a0, a0, a1 86 ; RV64I-NEXT: addw a0, a0, a1 97 ; RV64I-NEXT: addw a0, a0, a1 [all …]
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D | mul.ll | 16 ; RV32I-NEXT: mv a1, a0 24 ; RV32IM-NEXT: mul a0, a0, a0 31 ; RV64I-NEXT: mv a1, a0 33 ; RV64I-NEXT: sext.w a0, a0 40 ; RV64IM-NEXT: mulw a0, a0, a0 58 ; RV32IM-NEXT: mul a0, a0, a1 66 ; RV64I-NEXT: sext.w a0, a0 73 ; RV64IM-NEXT: mulw a0, a0, a1 82 ; RV32I-NEXT: slli a1, a0, 2 83 ; RV32I-NEXT: add a0, a1, a0 [all …]
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D | alu16.ll | 14 ; RV32I-NEXT: addi a0, a0, 1 19 ; RV64I-NEXT: addi a0, a0, 1 28 ; RV32I-NEXT: slli a0, a0, 16 29 ; RV32I-NEXT: srai a0, a0, 16 30 ; RV32I-NEXT: slti a0, a0, 2 35 ; RV64I-NEXT: slli a0, a0, 48 36 ; RV64I-NEXT: srai a0, a0, 48 37 ; RV64I-NEXT: slti a0, a0, 2 49 ; RV32I-NEXT: and a0, a0, a1 50 ; RV32I-NEXT: sltiu a0, a0, 3 [all …]
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D | rv64Zbs.ll | 15 ; RV64I-NEXT: and a0, a1, a0 20 ; RV64IB-NEXT: sbclrw a0, a0, a1 25 ; RV64IBS-NEXT: sbclrw a0, a0, a1 40 ; RV64I-NEXT: and a0, a1, a0 45 ; RV64IB-NEXT: sbclrw a0, a0, a1 50 ; RV64IBS-NEXT: sbclrw a0, a0, a1 61 ; RV64I-NEXT: lw a0, 0(a0) 65 ; RV64I-NEXT: and a0, a1, a0 66 ; RV64I-NEXT: sext.w a0, a0 71 ; RV64IB-NEXT: lw a0, 0(a0) [all …]
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D | rv32Zbb.ll | 12 ; RV32I-NEXT: not a0, a0 13 ; RV32I-NEXT: sll a0, a0, a1 14 ; RV32I-NEXT: not a0, a0 19 ; RV32IB-NEXT: slo a0, a0, a1 24 ; RV32IBB-NEXT: slo a0, a0, a1 41 ; RV32I-NEXT: not a0, a0 45 ; RV32I-NEXT: sll a1, a0, a3 52 ; RV32I-NEXT: srli a4, a0, 1 55 ; RV32I-NEXT: sll a2, a0, a2 58 ; RV32I-NEXT: not a0, a2 [all …]
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D | rv64Zbt.ll | 12 ; RV64I-NEXT: and a0, a1, a0 15 ; RV64I-NEXT: or a0, a1, a0 20 ; RV64IB-NEXT: cmix a0, a1, a0, a2 25 ; RV64IBT-NEXT: cmix a0, a1, a0, a2 37 ; RV64I-NEXT: and a0, a1, a0 40 ; RV64I-NEXT: or a0, a1, a0 45 ; RV64IB-NEXT: cmix a0, a1, a0, a2 50 ; RV64IBT-NEXT: cmix a0, a1, a0, a2 64 ; RV64I-NEXT: mv a2, a0 66 ; RV64I-NEXT: mv a0, a2 [all …]
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D | rv32Zbp.ll | 12 ; RV32I-NEXT: slli a1, a0, 1 16 ; RV32I-NEXT: srli a2, a0, 1 20 ; RV32I-NEXT: or a0, a2, a0 21 ; RV32I-NEXT: or a0, a0, a1 26 ; RV32IB-NEXT: orc.p a0, a0 31 ; RV32IBP-NEXT: orc.p a0, a0 45 ; RV32I-NEXT: slli a2, a0, 1 52 ; RV32I-NEXT: srli a5, a0, 1 58 ; RV32I-NEXT: or a0, a5, a0 59 ; RV32I-NEXT: or a0, a0, a2 [all …]
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D | rv64Zbp.ll | 12 ; RV64I-NEXT: slli a1, a0, 1 18 ; RV64I-NEXT: srli a2, a0, 1 22 ; RV64I-NEXT: or a0, a2, a0 23 ; RV64I-NEXT: or a0, a0, a1 24 ; RV64I-NEXT: sext.w a0, a0 29 ; RV64IB-NEXT: gorciw a0, a0, 1 34 ; RV64IBP-NEXT: gorciw a0, a0, 1 48 ; RV64I-NEXT: slli a1, a0, 1 58 ; RV64I-NEXT: srli a2, a0, 1 68 ; RV64I-NEXT: or a0, a2, a0 [all …]
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D | add-imm.ll | 12 ; RV32I-NEXT: addi a0, a0, 2047 17 ; RV64I-NEXT: addi a0, a0, 2047 26 ; RV32I-NEXT: addi a0, a0, 1024 27 ; RV32I-NEXT: addi a0, a0, 1024 32 ; RV64I-NEXT: addi a0, a0, 1024 33 ; RV64I-NEXT: addi a0, a0, 1024 42 ; RV32I-NEXT: addi a0, a0, 2047 43 ; RV32I-NEXT: addi a0, a0, 2047 48 ; RV64I-NEXT: addi a0, a0, 2047 49 ; RV64I-NEXT: addi a0, a0, 2047 [all …]
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D | alu32.ll | 19 ; RV32I-NEXT: addi a0, a0, 1 24 ; RV64I-NEXT: addi a0, a0, 1 33 ; RV32I-NEXT: slti a0, a0, 2 38 ; RV64I-NEXT: sext.w a0, a0 39 ; RV64I-NEXT: slti a0, a0, 2 49 ; RV32I-NEXT: sltiu a0, a0, 3 54 ; RV64I-NEXT: sext.w a0, a0 55 ; RV64I-NEXT: sltiu a0, a0, 3 65 ; RV32I-NEXT: xori a0, a0, 4 70 ; RV64I-NEXT: xori a0, a0, 4 [all …]
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D | alu64.ll | 17 ; RV64I-NEXT: addi a0, a0, 1 22 ; RV32I-NEXT: addi a2, a0, 1 23 ; RV32I-NEXT: sltu a0, a2, a0 24 ; RV32I-NEXT: add a1, a1, a0 25 ; RV32I-NEXT: mv a0, a2 34 ; RV64I-NEXT: slti a0, a0, 2 41 ; RV32I-NEXT: slti a0, a1, 0 45 ; RV32I-NEXT: sltiu a0, a0, 2 56 ; RV64I-NEXT: sltiu a0, a0, 3 63 ; RV32I-NEXT: mv a0, zero [all …]
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D | callee-saved-gprs.ll | 46 ; RV32I-NEXT: lw a0, %lo(var)(a7) 47 ; RV32I-NEXT: sw a0, 24(sp) 48 ; RV32I-NEXT: lw a0, %lo(var+4)(a7) 49 ; RV32I-NEXT: sw a0, 20(sp) 50 ; RV32I-NEXT: lw a0, %lo(var+8)(a7) 51 ; RV32I-NEXT: sw a0, 16(sp) 52 ; RV32I-NEXT: lw a0, %lo(var+12)(a7) 53 ; RV32I-NEXT: sw a0, 12(sp) 55 ; RV32I-NEXT: lw a0, 16(a5) 56 ; RV32I-NEXT: sw a0, 8(sp) [all …]
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D | add-before-shl.ll | 13 ; RV32I-NEXT: addi a0, a0, 1 14 ; RV32I-NEXT: slli a0, a0, 24 15 ; RV32I-NEXT: srai a0, a0, 24 20 ; RV64I-NEXT: addi a0, a0, 1 21 ; RV64I-NEXT: slli a0, a0, 56 22 ; RV64I-NEXT: srai a0, a0, 56 33 ; RV32I-NEXT: slli a0, a0, 16 35 ; RV32I-NEXT: add a0, a0, a1 36 ; RV32I-NEXT: srai a0, a0, 16 43 ; RV64I-NEXT: add a0, a0, a1 [all …]
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D | float-select-fcmp.ll | 10 ; RV32IF-NEXT: mv a0, a1 15 ; RV64IF-NEXT: mv a0, a1 26 ; RV32IF-NEXT: fmv.w.x ft0, a0 27 ; RV32IF-NEXT: feq.s a0, ft0, ft1 28 ; RV32IF-NEXT: bnez a0, .LBB1_2 32 ; RV32IF-NEXT: fmv.x.w a0, ft0 38 ; RV64IF-NEXT: fmv.w.x ft0, a0 39 ; RV64IF-NEXT: feq.s a0, ft0, ft1 40 ; RV64IF-NEXT: bnez a0, .LBB1_2 44 ; RV64IF-NEXT: fmv.x.w a0, ft0 [all …]
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/external/clang/test/CodeGen/ |
D | bitfield-2.c | 24 int f0_load(struct s0 *a0) { in f0_load() argument 26 return a0->f0; in f0_load() 28 int f0_store(struct s0 *a0) { in f0_store() argument 29 return (a0->f0 = 1); in f0_store() 31 int f0_reload(struct s0 *a0) { in f0_reload() argument 32 return (a0->f0 += 1); in f0_reload() 70 int f1_load(struct s1 *a0) { in f1_load() argument 72 return a0->f1; in f1_load() 74 int f1_store(struct s1 *a0) { in f1_store() argument 75 return (a0->f1 = 1234); in f1_store() [all …]
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/external/llvm-project/clang/test/CodeGen/ |
D | bitfield-2.c | 24 int f0_load(struct s0 *a0) { in f0_load() argument 26 return a0->f0; in f0_load() 28 int f0_store(struct s0 *a0) { in f0_store() argument 29 return (a0->f0 = 1); in f0_store() 31 int f0_reload(struct s0 *a0) { in f0_reload() argument 32 return (a0->f0 += 1); in f0_reload() 70 int f1_load(struct s1 *a0) { in f1_load() argument 72 return a0->f1; in f1_load() 74 int f1_store(struct s1 *a0) { in f1_store() argument 75 return (a0->f1 = 1234); in f1_store() [all …]
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/external/llvm-project/llvm/test/MC/RISCV/ |
D | numeric-reg-names.s | 9 addi a0, x0, 1 10 addi a0, zero, 1 14 addi a0, x1, 1 15 addi a0, ra, 1 19 addi a0, x2, 1 20 addi a0, sp, 1 24 addi a0, x3, 1 25 addi a0, gp, 1 29 addi a0, x4, 1 30 addi a0, tp, 1 [all …]
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