| /external/llvm/test/CodeGen/AMDGPU/ |
| D | shl_add_ptr.ll | 22 define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
27 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
42 define void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
48 store i32 %shl_add_use, i32 addrspace(1)* %add_use, align 4
58 …_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %lds, i32 addrspace(1)* %add_use) #0 {
63 store i32 %idx.0, i32 addrspace(1)* %add_use
92 define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
97 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
107 ; define void @atomic_load_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
113 ; store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
[all …]
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| D | llvm.amdgcn.atomic.inc.ll | 118 define void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
123 store i32 %idx.0, i32 addrspace(1)* %add_use
300 define void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
305 store i32 %idx.0, i32 addrspace(1)* %add_use
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| D | llvm.amdgcn.atomic.dec.ll | 243 define void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
248 store i32 %idx.0, i32 addrspace(1)* %add_use
366 define void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
371 store i32 %idx.0, i32 addrspace(1)* %add_use
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | shl_add_ptr.ll | 22 define amdgpu_kernel void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use…
27 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
46 define amdgpu_kernel void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %add_use…
52 store i32 %shl_add_use, i32 addrspace(1)* %add_use, align 4
62 …_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %lds, i32 addrspace(1)* %add_use) #0 {
67 store i32 %idx.0, i32 addrspace(1)* %add_use
104 …amdgpu_kernel void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
109 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
119 …pu_kernel void @atomic_load_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
125 ; store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
[all …]
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| D | llvm.amdgcn.atomic.inc.ll | 144 …kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
149 store i32 %idx.0, i32 addrspace(1)* %add_use
345 …kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
350 store i32 %idx.0, i32 addrspace(1)* %add_use
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| D | llvm.amdgcn.atomic.dec.ll | 284 …gpu_kernel void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
289 store i32 %idx.0, i32 addrspace(1)* %add_use
437 …kernel void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
442 store i32 %idx.0, i32 addrspace(1)* %add_use
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| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_def_use.cpp | 116 v->rel->add_use(n); in process_uses()
124 v->add_use(n); in process_uses()
127 v->add_use(n); in process_uses()
136 v->rel->add_use(n); in process_uses()
143 v->add_use(n); in process_uses()
148 n->pred->add_use(n); in process_uses()
153 i->cond->add_use(i); in process_uses()
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| D | sb_valtable.cpp | 219 void value::add_use(node* n) { in add_use() function in r600_sb::value
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| D | sb_ir.h | 582 void add_use(node *n);
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| /external/python/cpython2/Lib/compiler/ |
| D | symbols.py | 48 def add_use(self, name): member in Scope
319 scope.add_use(node.name)
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | llvm.amdgcn.atomic.inc.ll | 460 …kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
511 store i32 %idx.0, i32 addrspace(1)* %add_use
1180 …kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
1234 store i32 %idx.0, i32 addrspace(1)* %add_use
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| D | llvm.amdgcn.atomic.dec.ll | 1121 …gpu_kernel void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
1176 store i32 %idx.0, i32 addrspace(1)* %add_use
1680 …kernel void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
1738 store i32 %idx.0, i32 addrspace(1)* %add_use
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