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/external/llvm-project/llvm/test/MC/AVR/
Dinst-andi.s7 andi r16, 255
8 andi r29, 190
9 andi r22, 172
10 andi r27, 92
12 andi r20, BAR
14 ; CHECK: andi r16, 255 ; encoding: [0x0f,0x7f]
15 ; CHECK: andi r29, 190 ; encoding: [0xde,0x7b]
16 ; CHECK: andi r22, 172 ; encoding: [0x6c,0x7a]
17 ; CHECK: andi r27, 92 ; encoding: [0xbc,0x75]
19 ; CHECK: andi r20, BAR ; encoding: [0x40'A',0x70]
[all …]
Dinst-cbr.s12 ; CHECK: andi r17, -209 ; encoding: [0x1f,0x72]
13 ; CHECK: andi r24, -191 ; encoding: [0x81,0x74]
14 ; CHECK: andi r20, -174 ; encoding: [0x42,0x75]
15 ; CHECK: andi r31, -1 ; encoding: [0xff,0x7f]
17 ; CHECK-INST: andi r17, 47
18 ; CHECK-INST: andi r24, 65
19 ; CHECK-INST: andi r20, 82
20 ; CHECK-INST: andi r31, 255
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dand.ll168 ; GP32: andi $2, $4, 4
170 ; GP64: andi $2, $4, 4
182 ; GP32: andi $2, $4, 4
184 ; GP64: andi $2, $4, 4
196 ; GP32: andi $2, $4, 4
198 ; GP64: andi $2, $4, 4
210 ; GP32: andi $3, $5, 4
213 ; GP64: andi $2, $4, 4
218 ; MM64: andi $2, $4, 4
228 ; GP32: andi $5, $7, 4
[all …]
Durem.ll40 ; NOT-R6: andi $[[T0:[0-9]+]], $5, 1
41 ; NOT-R6: andi $[[T1:[0-9]+]], $4, 1
48 ; R6: andi $[[T0:[0-9]+]], $5, 1
49 ; R6: andi $[[T1:[0-9]+]], $4, 1
78 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255
79 ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 255
86 ; R2-R5: andi $[[T0:[0-9]+]], $5, 255
87 ; R2-R5: andi $[[T1:[0-9]+]], $4, 255
93 ; R6: andi $[[T0:[0-9]+]], $5, 255
94 ; R6: andi $[[T1:[0-9]+]], $4, 255
[all …]
Dselect-int.ll37 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
45 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
49 ; SEL: andi $[[T0:[0-9]+]], $4, 1
72 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
80 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
84 ; SEL: andi $[[T0:[0-9]+]], $4, 1
107 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
115 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
119 ; SEL: andi $[[T0:[0-9]+]], $4, 1
142 ; M2: andi $[[T0:[0-9]+]], $4, 1
[all …]
/external/llvm-project/llvm/test/CodeGen/AVR/
DPR31345.ll7 ; CHECK: andi {{r[0-9]+}}, 0
8 ; CHECK-NOT: andi {{r[0-9]+}}, 255
15 ; CHECK: andi {{r[0-9]+}}, 179
16 ; CHECK-NOT: andi {{r[0-9]+}}, 255
23 ; CHECK-NOT: andi {{r[0-9]+}}, 255
24 ; CHECK: andi {{r[0-9]+}}, 0
31 ; CHECK-NOT: andi {{r[0-9]+}}, 255
32 ; CHECK: andi {{r[0-9]+}}, 179
39 ; CHECK-NOT: andi {{r[0-9]+}}, 255
40 ; CHECK-NOT: andi {{r[0-9]+}}, 255
[all …]
Dand.ll12 ; CHECK: andi r24, 5
27 ; CHECK: andi r24, 210
28 ; CHECK: andi r25, 4
45 ; CHECK: andi r22, 21
46 ; CHECK: andi r23, 205
47 ; CHECK: andi r24, 91
48 ; CHECK: andi r25, 7
69 ; CHECK: andi r18, 253
71 ; CHECK-NOT: andi r19, 255
72 ; CHECK: andi r20, 155
[all …]
Dctpop.ll14 ; CHECK: andi {{.*}}[[SCRATCH]], 85
17 ; CHECK: andi {{.*}}[[SCRATCH]], 51
20 ; CHECK: andi {{.*}}[[RESULT]], 51
28 ; CHECK: andi {{.*}}[[SCRATCH]], 15
/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dand.ll409 ; MIPS-NEXT: andi $2, $4, 4
414 ; MIPS32R2-NEXT: andi $2, $4, 4
419 ; MIPS32R6-NEXT: andi $2, $4, 4
424 ; MIPS64-NEXT: andi $2, $4, 4
429 ; MIPS64R2-NEXT: andi $2, $4, 4
434 ; MIPS64R6-NEXT: andi $2, $4, 4
454 ; MIPS-NEXT: andi $2, $4, 4
459 ; MIPS32R2-NEXT: andi $2, $4, 4
464 ; MIPS32R6-NEXT: andi $2, $4, 4
469 ; MIPS64-NEXT: andi $2, $4, 4
[all …]
Dselect-int.ll37 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
46 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
50 ; SEL: andi $[[T0:[0-9]+]], $4, 1
73 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
82 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
86 ; SEL: andi $[[T0:[0-9]+]], $4, 1
109 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
118 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
122 ; SEL: andi $[[T0:[0-9]+]], $4, 1
146 ; M2: andi $[[T0:[0-9]+]], $4, 1
[all …]
Dashr.ll91 ; MIPS-NEXT: andi $1, $5, 255
97 ; MIPS32-NEXT: andi $1, $5, 255
103 ; 32R2-NEXT: andi $1, $5, 255
109 ; 32R6-NEXT: andi $1, $5, 255
115 ; MIPS3-NEXT: andi $1, $5, 255
121 ; MIPS64-NEXT: andi $1, $5, 255
127 ; MIPS64R2-NEXT: andi $1, $5, 255
133 ; MIPS64R6-NEXT: andi $1, $5, 255
149 ; FIXME: The andi instruction is redundant.
157 ; MIPS-NEXT: andi $1, $5, 65535
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/
Dbricmpi1.ll6 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
7 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
23 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
24 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
40 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
41 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
58 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
59 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
76 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
77 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
Dfunnel-shift-rot.ll23 ; CHECK-NEXT: andi $2, $4, 224
50 ; CHECK-NEXT: andi $1, $5, 15
53 ; CHECK-NEXT: andi $2, $2, 15
54 ; CHECK-NEXT: andi $3, $4, 65535
65 ; CHECK-NEXT: andi $1, $5, 31
68 ; CHECK-NEXT: andi $2, $2, 31
80 ; CHECK-BE-NEXT: andi $3, $1, 63
82 ; CHECK-BE-NEXT: andi $1, $1, 32
83 ; CHECK-BE-NEXT: andi $2, $7, 63
92 ; CHECK-BE-NEXT: andi $7, $7, 32
[all …]
Dfcmp.ll50 ; 32-CMP-DAG: andi $2, $[[T1]], 1
54 ; 64-CMP-DAG: andi $2, $[[T1]], 1
83 ; 32-CMP-DAG: andi $2, $[[T1]], 1
87 ; 64-CMP-DAG: andi $2, $[[T1]], 1
116 ; 32-CMP-DAG: andi $2, $[[T1]], 1
120 ; 64-CMP-DAG: andi $2, $[[T1]], 1
149 ; 32-CMP-DAG: andi $2, $[[T1]], 1
153 ; 64-CMP-DAG: andi $2, $[[T1]], 1
182 ; 32-CMP-DAG: andi $2, $[[T1]], 1
186 ; 64-CMP-DAG: andi $2, $[[T1]], 1
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dselect_const.ll192 ; ISEL-NEXT: andi. 3, 3, 1
200 ; NO_ISEL-NEXT: andi. 3, 3, 1
215 ; ISEL-NEXT: andi. 3, 3, 1
223 ; NO_ISEL-NEXT: andi. 3, 3, 1
238 ; ISEL-NEXT: andi. 3, 3, 1
246 ; NO_ISEL-NEXT: andi. 3, 3, 1
263 ; ISEL-NEXT: andi. 3, 3, 1
271 ; NO_ISEL-NEXT: andi. 3, 3, 1
287 ; ISEL-NEXT: andi. 3, 3, 1
295 ; NO_ISEL-NEXT: andi. 3, 3, 1
[all …]
Dpopcnt-zext.ll16 ; SLOW-NEXT: andi. 3, 3, 85
23 ; SLOW-NEXT: andi. 5, 5, 13107
52 ; SLOW-NEXT: andi. 3, 3, 85
59 ; SLOW-NEXT: andi. 5, 5, 13107
88 ; SLOW-NEXT: andi. 3, 3, 85
95 ; SLOW-NEXT: andi. 5, 5, 13107
124 ; SLOW-NEXT: andi. 3, 3, 85
131 ; SLOW-NEXT: andi. 5, 5, 13107
160 ; SLOW-NEXT: andi. 3, 3, 21845
167 ; SLOW-NEXT: andi. 5, 5, 13107
[all …]
Dcrbit-asm.ll17 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
20 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
40 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
43 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
56 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
59 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
/external/llvm-project/llvm/test/CodeGen/RISCV/
Dsext-zext-trunc.ll10 ; RV32I-NEXT: andi a0, a0, 1
16 ; RV64I-NEXT: andi a0, a0, 1
26 ; RV32I-NEXT: andi a0, a0, 1
32 ; RV64I-NEXT: andi a0, a0, 1
42 ; RV32I-NEXT: andi a0, a0, 1
48 ; RV64I-NEXT: andi a0, a0, 1
58 ; RV32I-NEXT: andi a0, a0, 1
65 ; RV64I-NEXT: andi a0, a0, 1
171 ; RV32I-NEXT: andi a0, a0, 1
176 ; RV64I-NEXT: andi a0, a0, 1
[all …]
Dalu8.ll47 ; RV32I-NEXT: andi a0, a0, 255
53 ; RV64I-NEXT: andi a0, a0, 255
89 define i8 @andi(i8 %a) nounwind {
90 ; RV32I-LABEL: andi:
92 ; RV32I-NEXT: andi a0, a0, 6
95 ; RV64I-LABEL: andi:
97 ; RV64I-NEXT: andi a0, a0, 6
120 ; RV32I-NEXT: andi a0, a0, 192
126 ; RV64I-NEXT: andi a0, a0, 192
218 ; RV32I-NEXT: andi a1, a1, 255
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Dselect.ll8 ; MIPS32-NEXT: andi $1, $4, 1
21 ; MIPS32-NEXT: andi $1, $4, 1
34 ; MIPS32-NEXT: andi $1, $4, 1
47 ; MIPS32-NEXT: andi $1, $4, 1
63 ; MIPS32-NEXT: andi $1, $1, 1
81 ; MIPS32-NEXT: andi $1, $4, 1
96 ; MIPS32-NEXT: andi $1, $4, 1
112 ; MIPS32-NEXT: andi $1, $4, 1
128 ; MIPS32-NEXT: andi $3, $4, 1
147 ; MIPS32-NEXT: andi $1, $1, 1
Dbswap.ll12 ; MIPS32-NEXT: andi $2, $4, 65280
16 ; MIPS32-NEXT: andi $2, $2, 65280
39 ; MIPS32-NEXT: andi $2, $5, 65280
43 ; MIPS32-NEXT: andi $2, $2, 65280
48 ; MIPS32-NEXT: andi $3, $4, 65280
52 ; MIPS32-NEXT: andi $3, $3, 65280
Dmul.ll31 ; MIPS32-NEXT: andi $2, $1, 255
67 ; MIPS32-NEXT: andi $2, $1, 65535
126 ; MIPS32-NEXT: andi $4, $4, 1
129 ; MIPS32-NEXT: andi $5, $5, 1
140 ; MIPS32-NEXT: andi $5, $5, 1
143 ; MIPS32-NEXT: andi $24, $24, 1
147 ; MIPS32-NEXT: andi $15, $15, 1
151 ; MIPS32-NEXT: andi $11, $11, 1
155 ; MIPS32-NEXT: andi $10, $10, 1
189 ; MIPS32-NEXT: andi $2, $2, 1
Dsub.ll32 ; MIPS32-NEXT: andi $2, $1, 255
68 ; MIPS32-NEXT: andi $2, $1, 65535
93 ; MIPS32-NEXT: andi $3, $3, 1
118 ; MIPS32-NEXT: andi $8, $4, 1
123 ; MIPS32-NEXT: andi $8, $8, 1
126 ; MIPS32-NEXT: andi $8, $6, 1
131 ; MIPS32-NEXT: andi $8, $8, 1
134 ; MIPS32-NEXT: andi $5, $5, 1
/external/llvm/test/CodeGen/PowerPC/
Dcrbit-asm.ll14 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
17 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
33 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
36 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
49 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
52 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
/external/llvm/test/CodeGen/Mips/
Dfcmp.ll52 ; 32-CMP-DAG: andi $2, $[[T1]], 1
56 ; 64-CMP-DAG: andi $2, $[[T1]], 1
86 ; 32-CMP-DAG: andi $2, $[[T1]], 1
90 ; 64-CMP-DAG: andi $2, $[[T1]], 1
120 ; 32-CMP-DAG: andi $2, $[[T1]], 1
124 ; 64-CMP-DAG: andi $2, $[[T1]], 1
154 ; 32-CMP-DAG: andi $2, $[[T1]], 1
158 ; 64-CMP-DAG: andi $2, $[[T1]], 1
188 ; 32-CMP-DAG: andi $2, $[[T1]], 1
192 ; 64-CMP-DAG: andi $2, $[[T1]], 1
[all …]

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