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Searched refs:areg (Results 1 – 9 of 9) sorted by relevance

/external/python/cpython2/Modules/_ctypes/libffi/src/xtensa/
Dffi.c256 int i, areg; in ffi_closure_SYSV_inner() local
262 areg = 0; in ffi_closure_SYSV_inner()
268 areg++; in ffi_closure_SYSV_inner()
277 if (arg_types[i]->alignment == 8 && (areg & 1) != 0) in ffi_closure_SYSV_inner()
278 areg++; in ffi_closure_SYSV_inner()
281 if (areg == FFI_REGISTER_NARGS) in ffi_closure_SYSV_inner()
282 areg += 4; in ffi_closure_SYSV_inner()
287 if (areg < FFI_REGISTER_NARGS && areg + numregs > FFI_REGISTER_NARGS) in ffi_closure_SYSV_inner()
288 areg = FFI_REGISTER_NARGS + 4; in ffi_closure_SYSV_inner()
291 avalue[i] = &values[areg]; in ffi_closure_SYSV_inner()
[all …]
/external/libffi/src/xtensa/
Dffi.c256 int i, areg; in ffi_closure_SYSV_inner() local
262 areg = 0; in ffi_closure_SYSV_inner()
268 areg++; in ffi_closure_SYSV_inner()
277 if (arg_types[i]->alignment == 8 && (areg & 1) != 0) in ffi_closure_SYSV_inner()
278 areg++; in ffi_closure_SYSV_inner()
281 if (areg == FFI_REGISTER_NARGS) in ffi_closure_SYSV_inner()
282 areg += 4; in ffi_closure_SYSV_inner()
287 if (areg < FFI_REGISTER_NARGS && areg + numregs > FFI_REGISTER_NARGS) in ffi_closure_SYSV_inner()
288 areg = FFI_REGISTER_NARGS + 4; in ffi_closure_SYSV_inner()
291 avalue[i] = &values[areg]; in ffi_closure_SYSV_inner()
[all …]
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_shader.cpp384 unsigned areg = a->base_gpr.sel(); in get_gpr_array() local
385 if (achan == chan && (reg >= areg && reg < areg+a->array_size)) in get_gpr_array()
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td920 Register areg, string operands,
926 let Uses = [areg];
927 let Defs = [areg, EFLAGS];
934 Register areg, string operands>
935 : BinOpAI<opcode, mnemonic, typeinfo, areg, operands,
937 let Uses = [areg, EFLAGS];
942 Register areg, string operands>
943 : BinOpAI<opcode, mnemonic, typeinfo, areg, operands> {
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrArithmetic.td894 Register areg, string operands, X86FoldableSchedWrite sched = WriteALU>
899 let Uses = [areg];
900 let Defs = [areg, EFLAGS];
907 Register areg, string operands>
908 : BinOpAI<opcode, mnemonic, typeinfo, areg, operands, WriteADC> {
909 let Uses = [areg, EFLAGS];
914 Register areg, string operands>
915 : BinOpAI<opcode, mnemonic, typeinfo, areg, operands> {
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrArithmetic.td894 Register areg, string operands, X86FoldableSchedWrite sched = WriteALU>
899 let Uses = [areg];
900 let Defs = [areg, EFLAGS];
907 Register areg, string operands>
908 : BinOpAI<opcode, mnemonic, typeinfo, areg, operands, WriteADC> {
909 let Uses = [areg, EFLAGS];
914 Register areg, string operands>
915 : BinOpAI<opcode, mnemonic, typeinfo, areg, operands> {
/external/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td1393 def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1492 def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td1676 def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1787 def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td1676 def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1787 def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),