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Searched refs:bfmlalb (Results 1 – 10 of 10) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dbfmlal.s6 bfmlalb z0.S, z1.H, z2.H label
16 bfmlalb z0.S, z1.H, z2.H[0] label
26 bfmlalb z0.S, z1.H, z2.H[7] label
41 bfmlalb z10.S, z21.H, z14.H label
51 bfmlalb z21.s, z14.h, z3.h[2] label
64 bfmlalb z0.S, z1.H, z2.H label
84 bfmlalb z0.S, z1.H, z2.H[0] label
104 bfmlalb z0.S, z1.H, z2.H[7] label
134 bfmlalb z10.S, z21.H, z14.H label
154 bfmlalb z21.s, z14.h, z3.h[2] label
Dbfmlal-diagnostics.s3 bfmlalb z0.S, z1.H, z7.H[8] label
8 bfmlalb z0.S, z1.H, z8.H[7] label
/external/llvm-project/llvm/test/MC/AArch64/
Darmv8.6a-bf16.s75 bfmlalb V10.4S, V21.8h, V14.8H label
86 bfmlalb V14.4S, V21.8H, V10.H[1] label
87 bfmlalb V14.4S, V21.8H, V10.H[2] label
88 bfmlalb V14.4S, V21.8H, V10.H[7] label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-bfloat.ll57 ; CHECK-NEXT: bfmlalb z0.s, z1.h, z2.h
59 …%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb(<vscale x 4 x float> %a, <vscale x 8 x …
65 ; CHECK-NEXT: bfmlalb z0.s, z1.h, z2.h[0]
67 …%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane(<vscale x 4 x float> %a, <vscale x…
73 ; CHECK-NEXT: bfmlalb z0.s, z1.h, z2.h[1]
75 …%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane(<vscale x 4 x float> %a, <vscale x…
81 ; CHECK-NEXT: bfmlalb z0.s, z1.h, z2.h[2]
83 …%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane(<vscale x 4 x float> %a, <vscale x…
89 ; CHECK-NEXT: bfmlalb z0.s, z1.h, z2.h[3]
91 …%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlalb.lane(<vscale x 4 x float> %a, <vscale x…
[all …]
Daarch64-bf16-dotprod-intrinsics.ll91 ; CHECK-NEXT: bfmlalb v0.4s, v1.8h, v2.8h
94 …%vbfmlalbq_v3.i = call <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 …
112 ; CHECK-NEXT: bfmlalb v0.4s, v1.8h, v2.h[0]
116 …%vbfmlalbq_v3.i = call <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 …
123 ; CHECK-NEXT: bfmlalb v0.4s, v1.8h, v2.h[3]
127 …%vbfmlalbq_v3.i = call <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 …
157 declare <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float>, <8 x bfloat>, <8 x bfloat>)
/external/llvm-project/llvm/test/Bitcode/
Daarch64-bf16-upgrade.ll47 …%vbfmlalb1.i = call <4 x float> @llvm.aarch64.neon.bfmlalb.v4f32.v16i8(<4 x float> %r, <16 x i8> %…
50 …; CHECK-NEXT: %vbfmlalb1.i = call <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float> %r, <8 x bflo…
73 declare <4 x float> @llvm.aarch64.neon.bfmlalb.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)
74 ; CHECK: declare <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float>, <8 x bfloat>, <8 x bfloat>)
Darm-bf16-upgrade.ll47 …%vbfmlalb1.i = call <4 x float> @llvm.arm.neon.bfmlalb.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <…
50 …; CHECK-NEXT: %vbfmlalb1.i = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> %r, <8 x bfloat> …
73 declare <4 x float> @llvm.arm.neon.bfmlalb.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)
74 ; CHECK: declare <4 x float> @llvm.arm.neon.bfmlalb(<4 x float>, <8 x bfloat>, <8 x bfloat>)
/external/llvm-project/llvm/test/CodeGen/ARM/
Darm-bf16-dotprod-intrinsics.ll94 …%vbfmlalbq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 x bf…
116 …%vbfmlalbq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 x bf…
127 …%vbfmlalbq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 x bf…
169 declare <4 x float> @llvm.arm.neon.bfmlalb(<4 x float>, <8 x bfloat>, <8 x bfloat>)
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1527 defm BFMMLA_B_ZZZ : sve_bfloat_matmul_longvecl<0b0, "bfmlalb", int_aarch64_sve_bfmlalb>;
1529 … defm BFMMLA_B_ZZI : sve_bfloat_matmul_longvecl_idx<0b0, "bfmlalb", int_aarch64_sve_bfmlalb_lane>;
DAArch64InstrInfo.td801 def BFMLALB : SIMDBF16MLAL<0, "bfmlalb", int_aarch64_neon_bfmlalb>;
803 def BFMLALBIdx : SIMDBF16MLALIndex<0, "bfmlalb", int_aarch64_neon_bfmlalb>;