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/external/llvm/test/MC/Mips/
Dmips-bad-branches.s140 # CHECK: bgezal $1, -131069
142 # CHECK: bgezal $1, -131070
144 # CHECK: bgezal $1, -131071
146 # CHECK: bgezal $1, -131073
148 # CHECK: bgezal $1, 131069
150 # CHECK: bgezal $1, 131070
152 # CHECK: bgezal $1, 131071
154 # CHECK: bgezal $1, 131072
339 bgezal $1, -131068
340 bgezal $1, -131069
[all …]
Dmicromips-bad-branches.s76 # CHECK: bgezal $1, -65535
78 # CHECK: bgezal $1, -65537
80 # CHECK: bgezal $1, 65535
82 # CHECK: bgezal $1, 65536
190 bgezal $1, -65535
191 bgezal $1, -65536
192 bgezal $1, -65537
193 bgezal $1, 65534
194 bgezal $1, 65535
195 bgezal $1, 65536
Dmicromips-branch-instructions.s18 # CHECK-EL: bgezal $6, 1332 # encoding: [0x66,0x40,0x9a,0x02]
45 # CHECK-EB: bgezal $6, 1332 # encoding: [0x40,0x66,0x02,0x9a]
71 bgezal $6,1332
Dmips-jump-instructions.s21 # CHECK32: bgezal $6, 1332 # encoding: [0x4d,0x01,0xd1,0x04]
46 # CHECK64: bgezal $6, 1332 # encoding: [0x4d,0x01,0xd1,0x04]
73 bgezal $6,1332
Dmips-jump-delay-slots.s22 # CHECK: bgezal $6, 1332
24 bgezal $6,1332
Dmicromips-branch-fixup.s50 # CHECK-FIXUP: bgezal $4, bar # encoding: [0x64'A',0x40'A',0x00,0x00]
90 bgezal $4, bar
/external/llvm-project/llvm/test/MC/Mips/
Dmips-bad-branches.s140 # CHECK: bgezal $1, -131069
142 # CHECK: bgezal $1, -131070
144 # CHECK: bgezal $1, -131071
146 # CHECK: bgezal $1, -131073
148 # CHECK: bgezal $1, 131069
150 # CHECK: bgezal $1, 131070
152 # CHECK: bgezal $1, 131071
154 # CHECK: bgezal $1, 131072
339 bgezal $1, -131068
340 bgezal $1, -131069
[all …]
Dmicromips-bad-branches.s76 # CHECK: bgezal $1, -65535
78 # CHECK: bgezal $1, -65537
80 # CHECK: bgezal $1, 65535
82 # CHECK: bgezal $1, 65536
190 bgezal $1, -65535
191 bgezal $1, -65536
192 bgezal $1, -65537
193 bgezal $1, 65534
194 bgezal $1, 65535
195 bgezal $1, 65536
Dmicromips-branch-instructions.s18 # CHECK-EL: bgezal $6, 1332 # encoding: [0x66,0x40,0x9a,0x02]
45 # CHECK-EB: bgezal $6, 1332 # encoding: [0x40,0x66,0x02,0x9a]
71 bgezal $6,1332
Dmips-jump-instructions.s21 # CHECK32: bgezal $6, 1332 # encoding: [0x4d,0x01,0xd1,0x04]
46 # CHECK64: bgezal $6, 1332 # encoding: [0x4d,0x01,0xd1,0x04]
73 bgezal $6,1332
Dmips-jump-delay-slots.s21 # CHECK: bgezal $6, 1332
23 bgezal $6,1332
Dmicromips-branch-fixup.s44 # CHECK-FIXUP: bgezal $4, bar # encoding: [0x64'A',0x40'A',0x00,0x00]
84 bgezal $4, bar
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips5.s8 …bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
9 …bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips4.s10 …bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips1.s11 …bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
12 …bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips3.s9 …bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
10 …bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips2.s14 …bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm-project/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips4.s10 …bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips5.s9 …bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
10 …bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips1.s11 …bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
12 …bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips3.s9 …bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
10 …bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
Dinvalid-mips2.s14 …bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/capstone/suite/MC/Mips/
Dmicromips-branch-instructions.s.cs5 0x66,0x40,0x9a,0x02 = bgezal $a2, 1332
Dmicromips-branch-instructions-EB.s.cs5 0x40,0x66,0x02,0x9a = bgezal $a2, 1332
/external/llvm/test/MC/Mips/mips1/
Dvalid.s24 bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
25 bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]

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