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Searched refs:bitsGT (Results 1 – 25 of 51) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DValueTypes.h200 bool bitsGT(EVT VT) const { in bitsGT() function
DMachineValueType.h532 bool bitsGT(MVT VT) const { in bitsGT() function
/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.cpp91 if (Src.getValueType().bitsGT(MVT::i32)) in EmitSpecializedLibcall()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.cpp90 if (Src.getValueType().bitsGT(MVT::i32)) in EmitSpecializedLibcall()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.h231 bool bitsGT(EVT VT) const { in bitsGT() function
/external/llvm-project/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.cpp90 if (Src.getValueType().bitsGT(MVT::i32)) in EmitSpecializedLibcall()
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.h246 bool bitsGT(EVT VT) const { in bitsGT() function
/external/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp137 if (AVT.bitsGT(MVT::i8)) { in EmitTargetCodeForMemset()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp138 if (AVT.bitsGT(MVT::i8)) { in EmitTargetCodeForMemset()
/external/llvm-project/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp142 if (AVT.bitsGT(MVT::i8)) { in EmitTargetCodeForMemset()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp1123 return VT.bitsGT(Op.getValueType()) in getFPExtendOrRound()
1134 VT.bitsGT(Op.getValueType()) in getStrictFPExtendOrRound()
1143 return VT.bitsGT(Op.getValueType()) ? in getAnyExtOrTrunc()
1149 return VT.bitsGT(Op.getValueType()) ? in getSExtOrTrunc()
1155 return VT.bitsGT(Op.getValueType()) ? in getZExtOrTrunc()
4349 if (SVT.bitsGT(VT.getScalarType())) in foldCONCAT_VECTORS()
4674 assert(Operand.getValueType().bitsGT(VT) && in getNode()
4684 if (Operand.getOperand(0).getValueType().bitsGT(VT)) in getNode()
4942 if (V1->getValueType(0).bitsGT(SVT)) in FoldConstantArithmetic()
4944 if (V2->getValueType(0).bitsGT(SVT)) in FoldConstantArithmetic()
[all …]
DFastISel.cpp522 } else if (IdxVT.bitsGT(PtrVT)) { in getRegForGEPIndex()
1900 if (DstVT.bitsGT(SrcVT)) in selectOperator()
DDAGCombiner.cpp4792 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) in isAndLoadExtLoad()
10755 if (N0.getOperand(0).getValueType().bitsGT(VT)) in visitTRUNCATE()
16951 ISD::LoadExtType ExtTy = ResultVT.bitsGT(VecEltVT) ? in scalarizeExtractedVectorLoad()
16987 if (ResultVT.bitsGT(VecEltVT)) { in scalarizeExtractedVectorLoad()
17234 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) in visitEXTRACT_VECTOR_ELT()
20269 if (XType.bitsGT(AType)) { in foldSelectCCToShiftAnd()
20289 if (XType.bitsGT(AType)) { in foldSelectCCToShiftAnd()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h863 bool bitsGT(MVT VT) const { in bitsGT() function
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp1002 return VT.bitsGT(Op.getValueType()) ? in getAnyExtOrTrunc()
1008 return VT.bitsGT(Op.getValueType()) ? in getSExtOrTrunc()
1014 return VT.bitsGT(Op.getValueType()) ? in getZExtOrTrunc()
2874 if (SVT.bitsGT(VT.getScalarType())) in FoldCONCAT_VECTORS()
3134 assert(Operand.getValueType().bitsGT(VT) && in getNode()
3144 if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT)) in getNode()
3437 if (ScalarVT.isInteger() && ScalarVT.bitsGT(InSVT)) in FoldConstantVectorArithmetic()
4224 if (VT.bitsGT(LVT)) in FindOptimalMemOpLowering()
4555 if (MemOps[i].bitsGT(LargestVT)) in getMemsetStores()
DFastISel.cpp332 } else if (IdxVT.bitsGT(PtrVT)) { in getRegForGEPIndex()
1655 if (DstVT.bitsGT(SrcVT)) in selectOperator()
DDAGCombiner.cpp3034 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) in isAndLoadExtLoad()
5114 if (VT.bitsGT(VT0)) in visitSELECT()
6302 if (VT.bitsGT(Op.getValueType())) in visitZERO_EXTEND()
6359 } else if (SrcVT.bitsGT(VT)) { in visitZERO_EXTEND()
6378 } else if (X.getValueType().bitsGT(VT)) { in visitZERO_EXTEND()
6605 if (TruncOp.getValueType().bitsGT(VT)) in visitANY_EXTEND()
6620 } else if (X.getValueType().bitsGT(VT)) { in visitANY_EXTEND()
7097 if (N0.getOperand(0).getValueType().bitsGT(VT)) in visitTRUNCATE()
12245 InVal = OpVT.bitsGT(InVal.getValueType()) ? in visitINSERT_VECTOR_ELT()
12297 if (ResultVT.bitsGT(VecEltVT)) { in ReplaceExtractVectorEltOfLoadWithNarrowedLoad()
[all …]
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp1174 return VT.bitsGT(Op.getValueType()) in getFPExtendOrRound()
1185 VT.bitsGT(Op.getValueType()) in getStrictFPExtendOrRound()
1194 return VT.bitsGT(Op.getValueType()) ? in getAnyExtOrTrunc()
1200 return VT.bitsGT(Op.getValueType()) ? in getSExtOrTrunc()
1206 return VT.bitsGT(Op.getValueType()) ? in getZExtOrTrunc()
4313 if (SVT.bitsGT(VT.getScalarType())) { in foldCONCAT_VECTORS()
4654 assert(Operand.getValueType().bitsGT(VT) && in getNode()
4664 if (Operand.getOperand(0).getValueType().bitsGT(VT)) in getNode()
4947 if (V1->getValueType(0).bitsGT(SVT)) in FoldConstantArithmetic()
4949 if (V2->getValueType(0).bitsGT(SVT)) in FoldConstantArithmetic()
[all …]
DFastISel.cpp536 } else if (IdxVT.bitsGT(PtrVT)) { in getRegForGEPIndex()
1962 if (DstVT.bitsGT(SrcVT)) in selectOperator()
DDAGCombiner.cpp5065 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) in isAndLoadExtLoad()
11741 if (N0.getOperand(0).getValueType().bitsGT(VT)) in visitTRUNCATE()
18081 ISD::LoadExtType ExtTy = ResultVT.bitsGT(VecEltVT) ? in scalarizeExtractedVectorLoad()
18117 if (ResultVT.bitsGT(VecEltVT)) { in scalarizeExtractedVectorLoad()
18389 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) in visitEXTRACT_VECTOR_ELT()
21704 if (XType.bitsGT(AType)) { in foldSelectCCToShiftAnd()
21724 if (XType.bitsGT(AType)) { in foldSelectCCToShiftAnd()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h1042 bool bitsGT(MVT VT) const { in bitsGT() function
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1680 return VT.bitsGT(MVT::i32) && Align % 4 == 0; in allowsMisalignedMemoryAccesses()
1927 InVal = OpVT.bitsGT(InVal.getValueType()) ? in PerformDAGCombine()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1686 return VT.bitsGT(MVT::i32) && Align % 4 == 0; in allowsMisalignedMemoryAccesses()
1933 InVal = OpVT.bitsGT(InVal.getValueType()) ? in PerformDAGCombine()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1834 return VT.bitsGT(MVT::i32) && Align % 4 == 0; in allowsMisalignedMemoryAccesses()
2037 InVal = OpVT.bitsGT(InVal.getValueType()) ? in PerformDAGCombine()
DSIISelLowering.cpp474 return VT.bitsGT(MVT::i32) && Align % 4 == 0; in allowsMisalignedMemoryAccesses()

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