/external/llvm-project/llvm/test/MC/Mips/msa/ |
D | test_cbranch.s | 3 #CHECK: bnz.b $w0, 4 # encoding: [0x47,0x80,0x00,0x01] 5 #CHECK: bnz.h $w1, 16 # encoding: [0x47,0xa1,0x00,0x04] 7 #CHECK: bnz.w $w2, 128 # encoding: [0x47,0xc2,0x00,0x20] 9 #CHECK: bnz.d $w3, -128 # encoding: [0x47,0xe3,0xff,0xe0] 10 #CHECK: bnz.b $w0, SYMBOL0 # encoding: [0x47,0x80,A,A] 13 #CHECK: bnz.h $w1, SYMBOL1 # encoding: [0x47,0xa1,A,A] 16 #CHECK: bnz.w $w2, SYMBOL2 # encoding: [0x47,0xc2,A,A] 19 #CHECK: bnz.d $w3, SYMBOL3 # encoding: [0x47,0xe3,A,A] 23 #CHECK: bnz.v $w0, 4 # encoding: [0x45,0xe0,0x00,0x01] 25 #CHECK: bnz.v $w0, SYMBOL0 # encoding: [0x45,0xe0,A,A] [all …]
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/external/llvm/test/MC/Mips/msa/ |
D | test_cbranch.s | 3 #CHECK: bnz.b $w0, 4 # encoding: [0x47,0x80,0x00,0x01] 5 #CHECK: bnz.h $w1, 16 # encoding: [0x47,0xa1,0x00,0x04] 7 #CHECK: bnz.w $w2, 128 # encoding: [0x47,0xc2,0x00,0x20] 9 #CHECK: bnz.d $w3, -128 # encoding: [0x47,0xe3,0xff,0xe0] 10 #CHECK: bnz.b $w0, SYMBOL0 # encoding: [0x47,0x80,A,A] 13 #CHECK: bnz.h $w1, SYMBOL1 # encoding: [0x47,0xa1,A,A] 16 #CHECK: bnz.w $w2, SYMBOL2 # encoding: [0x47,0xc2,A,A] 19 #CHECK: bnz.d $w3, SYMBOL3 # encoding: [0x47,0xe3,A,A] 23 #CHECK: bnz.v $w0, 4 # encoding: [0x45,0xe0,0x00,0x01] 25 #CHECK: bnz.v $w0, SYMBOL0 # encoding: [0x45,0xe0,A,A] [all …]
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/external/llvm/test/CodeGen/Mips/msa/ |
D | i10.ll | 11 %1 = tail call i32 @llvm.mips.bnz.b(<16 x i8> %0) 20 declare i32 @llvm.mips.bnz.b(<16 x i8>) nounwind 24 ; CHECK-DAG: bnz.b [[R0]] 32 %1 = tail call i32 @llvm.mips.bnz.h(<8 x i16> %0) 41 declare i32 @llvm.mips.bnz.h(<8 x i16>) nounwind 45 ; CHECK-DAG: bnz.h [[R0]] 53 %1 = tail call i32 @llvm.mips.bnz.w(<4 x i32> %0) 62 declare i32 @llvm.mips.bnz.w(<4 x i32>) nounwind 66 ; CHECK-DAG: bnz.w [[R0]] 74 %1 = tail call i32 @llvm.mips.bnz.d(<2 x i64> %0) [all …]
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D | vecs10.ll | 11 %1 = tail call i32 @llvm.mips.bnz.v(<16 x i8> %0) 20 declare i32 @llvm.mips.bnz.v(<16 x i8>) nounwind 24 ; CHECK-DAG: bnz.v [[R0]]
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/external/llvm-project/llvm/test/CodeGen/Mips/msa/ |
D | i10.ll | 11 %1 = tail call i32 @llvm.mips.bnz.b(<16 x i8> %0) 20 declare i32 @llvm.mips.bnz.b(<16 x i8>) nounwind 24 ; CHECK-DAG: bnz.b [[R0]] 32 %1 = tail call i32 @llvm.mips.bnz.h(<8 x i16> %0) 41 declare i32 @llvm.mips.bnz.h(<8 x i16>) nounwind 45 ; CHECK-DAG: bnz.h [[R0]] 53 %1 = tail call i32 @llvm.mips.bnz.w(<4 x i32> %0) 62 declare i32 @llvm.mips.bnz.w(<4 x i32>) nounwind 66 ; CHECK-DAG: bnz.w [[R0]] 74 %1 = tail call i32 @llvm.mips.bnz.d(<2 x i64> %0) [all …]
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D | vecs10.ll | 11 %1 = tail call i32 @llvm.mips.bnz.v(<16 x i8> %0) 20 declare i32 @llvm.mips.bnz.v(<16 x i8>) nounwind 24 ; CHECK-DAG: bnz.v [[R0]]
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/external/llvm-project/lldb/source/Plugins/Instruction/MIPS64/ |
D | EmulateInstructionMIPS64.h | 161 bool bnz); 167 bool Emulate_MSA_Branch_V(llvm::MCInst &insn, bool bnz);
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D | EmulateInstructionMIPS64.cpp | 2191 bool bnz) { in Emulate_MSA_Branch_DF() argument 2213 if ((*ptr == 0 && bnz) || (*ptr != 0 && !bnz)) in Emulate_MSA_Branch_DF() 2217 if ((*(const uint16_t *)ptr == 0 && bnz) || in Emulate_MSA_Branch_DF() 2218 (*(const uint16_t *)ptr != 0 && !bnz)) in Emulate_MSA_Branch_DF() 2222 if ((*(const uint32_t *)ptr == 0 && bnz) || in Emulate_MSA_Branch_DF() 2223 (*(const uint32_t *)ptr != 0 && !bnz)) in Emulate_MSA_Branch_DF() 2227 if ((*(const uint64_t *)ptr == 0 && bnz) || in Emulate_MSA_Branch_DF() 2228 (*(const uint64_t *)ptr != 0 && !bnz)) in Emulate_MSA_Branch_DF() 2258 bool bnz) { in Emulate_MSA_Branch_V() argument 2279 if ((llvm::APInt::isSameValue(zero_value, wr_val) && !bnz) || in Emulate_MSA_Branch_V() [all …]
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/external/llvm-project/lldb/source/Plugins/Instruction/MIPS/ |
D | EmulateInstructionMIPS.h | 186 bool bnz); 192 bool Emulate_MSA_Branch_V(llvm::MCInst &insn, bool bnz);
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D | EmulateInstructionMIPS.cpp | 2878 bool bnz) { in Emulate_MSA_Branch_DF() argument 2900 if ((*ptr == 0 && bnz) || (*ptr != 0 && !bnz)) in Emulate_MSA_Branch_DF() 2904 if ((*(const uint16_t *)ptr == 0 && bnz) || in Emulate_MSA_Branch_DF() 2905 (*(const uint16_t *)ptr != 0 && !bnz)) in Emulate_MSA_Branch_DF() 2909 if ((*(const uint32_t *)ptr == 0 && bnz) || in Emulate_MSA_Branch_DF() 2910 (*(const uint32_t *)ptr != 0 && !bnz)) in Emulate_MSA_Branch_DF() 2914 if ((*(const uint64_t *)ptr == 0 && bnz) || in Emulate_MSA_Branch_DF() 2915 (*(const uint64_t *)ptr != 0 && !bnz)) in Emulate_MSA_Branch_DF() 2945 bool bnz) { in Emulate_MSA_Branch_V() argument 2966 if ((llvm::APInt::isSameValue(zero_value, wr_val) && !bnz) || in Emulate_MSA_Branch_V() [all …]
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/external/llvm-project/llvm/test/CodeGen/Mips/longbranch/ |
D | branch-limits-msa.mir | 123 %2 = tail call i32 @llvm.mips.bnz.b(<16 x i8> %d.8.vecblend) 136 declare i32 @llvm.mips.bnz.b(<16 x i8>) 145 %2 = tail call i32 @llvm.mips.bnz.h(<8 x i16> %d.8.vecblend) 158 declare i32 @llvm.mips.bnz.h(<8 x i16>) 167 %2 = tail call i32 @llvm.mips.bnz.w(<4 x i32> %d.8.vecblend) 180 declare i32 @llvm.mips.bnz.w(<4 x i32>) 186 %0 = tail call i32 @llvm.mips.bnz.d(<2 x i64> %d.8.vec.insert) 199 declare i32 @llvm.mips.bnz.d(<2 x i64>) 206 %0 = tail call i32 @llvm.mips.bnz.v(<16 x i8> %d.16.vec.insert) 219 declare i32 @llvm.mips.bnz.v(<16 x i8>)
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/external/openscreen/third_party/boringssl/ios-arm/crypto/fipsmodule/ |
D | vpaes-armv7.S | 125 @ .Lenc_entry ends with a bnz instruction which is normally paired with
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/external/rust/crates/quiche/deps/boringssl/ios-arm/crypto/fipsmodule/ |
D | vpaes-armv7.S | 125 @ .Lenc_entry ends with a bnz instruction which is normally paired with
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/external/boringssl/ios-arm/crypto/fipsmodule/ |
D | vpaes-armv7.S | 125 @ .Lenc_entry ends with a bnz instruction which is normally paired with
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/external/openscreen/third_party/boringssl/linux-arm/crypto/fipsmodule/ |
D | vpaes-armv7.S | 122 @ .Lenc_entry ends with a bnz instruction which is normally paired with
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/external/rust/crates/quiche/deps/boringssl/linux-arm/crypto/fipsmodule/ |
D | vpaes-armv7.S | 122 @ .Lenc_entry ends with a bnz instruction which is normally paired with
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/external/boringssl/linux-arm/crypto/fipsmodule/ |
D | vpaes-armv7.S | 122 @ .Lenc_entry ends with a bnz instruction which is normally paired with
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
D | MipsGenAsmMatcher.inc | 4955 "c16\005bnezl\004bnvc\005bnz.b\005bnz.d\005bnz.h\005bnz.v\005bnz.w\004bo" 5826 …{ 1538 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, … 5827 …{ 1544 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, … 5828 …{ 1550 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, … 5829 …{ 1556 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, … 5830 …{ 1562 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, … 8852 { 1538 /* bnz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8853 { 1538 /* bnz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, 8854 { 1544 /* bnz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, 8855 { 1544 /* bnz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, [all …]
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/external/llvm-project/llvm/test/MC/Sparc/ |
D | sparc-ctrl-instructions.s | 57 bnz .BB0
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/external/llvm/test/MC/Sparc/ |
D | sparc-ctrl-instructions.s | 57 bnz .BB0
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/external/rust/crates/ring/pregenerated/ |
D | vpaes-armv7-ios32.S | 122 @ .Lenc_entry ends with a bnz instruction which is normally paired with
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D | vpaes-armv7-linux32.S | 119 @ .Lenc_entry ends with a bnz instruction which is normally paired with
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/external/llvm/lib/Target/Mips/ |
D | MipsMSAInstrInfo.td | 1711 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; 1712 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; 1713 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; 1714 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; 1716 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsScheduleP5600.td | 310 // bnz.[bhwdv], cfcmsa, ctcmsa
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/external/llvm-project/llvm/lib/Target/Mips/ |
D | MipsScheduleP5600.td | 311 // bnz.[bhwdv], cfcmsa, ctcmsa
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