| /external/mesa3d/src/amd/vulkan/ |
| D | radv_cs.h | 38 if (cs->max_dw - cs->cdw < needed) in radeon_check_space()
40 return cs->cdw + needed; in radeon_check_space()
46 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_config_reg_seq()
61 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_context_reg_seq()
79 assert(cs->cdw + 3 <= cs->max_dw); in radeon_set_context_reg_idx()
90 assert(cs->cdw + 4 <= cs->max_dw); in radeon_set_context_reg_rmw()
100 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_sh_reg_seq()
118 assert(cs->cdw + 3 <= cs->max_dw); in radeon_set_sh_reg_idx()
133 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_uconfig_reg_seq()
143 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_uconfig_reg_seq_perfctr()
[all …]
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| D | radv_radeon_winsys.h | 99 unsigned cdw; /* Number of used dwords. */ member
350 cs->buf[cs->cdw++] = value; in radeon_emit()
356 memcpy(cs->buf + cs->cdw, values, count * 4); in radeon_emit_array()
357 cs->cdw += count; in radeon_emit_array()
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| /external/mesa3d/src/gallium/drivers/r300/ |
| D | r300_cs.h | 49 assert(size <= (cs_copy->current.max_dw - cs_copy->current.cdw)); \
75 cs_copy->current.buf[cs_copy->current.cdw++] = (value); \
99 memcpy(cs_copy->current.buf + cs_copy->current.cdw, (values), (count) * 4); \
100 cs_copy->current.cdw += (count); \
123 memcpy(cs_copy->current.buf + cs_copy->current.cdw, (values), (count) * 4); \
124 cs_copy->current.cdw += (count); \
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| /external/libdrm/radeon/ |
| D | radeon_cs.h | 55 unsigned cdw; member
117 cs->packets[cs->cdw++] = dword; in radeon_cs_write_dword()
125 memcpy(cs->packets + cs->cdw, &qword, sizeof(uint64_t)); in radeon_cs_write_qword()
126 cs->cdw += 2; in radeon_cs_write_qword()
135 memcpy(cs->packets + cs->cdw, data, size * 4); in radeon_cs_write_table()
136 cs->cdw += size; in radeon_cs_write_table()
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| D | radeon_cs_gem.c | 296 if (cs->cdw + ndw > cs->ndw) { in cs_gem_begin()
300 tmp = (cs->cdw + ndw + 0x3FF) & (~0x3FF); in cs_gem_begin()
366 blob = bof_blob(cs->cdw * 4, cs->packets); in cs_gem_dump_bof()
431 while (cs->cdw & 7) in cs_gem_emit()
437 csg->chunks[0].length_dw = cs->cdw; in cs_gem_emit()
489 cs->cdw = 0; in cs_gem_erase()
509 for (i = 0; i < cs->cdw; i++) { in cs_gem_print()
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| D | radeon_cs_int.h | 15 unsigned cdw; member
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| /external/virglrenderer/tests/ |
| D | testvirgl_encode.h | 39 state->buf[state->cdw++] = dword; in virgl_encoder_write_dword()
45 memcpy(state->buf + state->cdw, &qword, sizeof(uint64_t)); in virgl_encoder_write_qword()
46 state->cdw += 2; in virgl_encoder_write_qword()
52 memcpy(state->buf + state->cdw, &qword, sizeof(double)); in virgl_encoder_write_double()
53 state->cdw += 2; in virgl_encoder_write_double()
60 memcpy(state->buf + state->cdw, ptr, len); in virgl_encoder_write_block()
64 uint8_t *mp = (uint8_t *)(state->buf + state->cdw); in virgl_encoder_write_block()
68 state->cdw += (len + 3) / 4; in virgl_encoder_write_block()
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| D | test_virgl_transfer.c | 707 ret = virgl_renderer_submit_cmd(ctx.cbuf->buf, ctx.ctx_id, ctx.cbuf->cdw); in virgl_test_transfer_inline()
752 ret = virgl_renderer_submit_cmd(ctx.cbuf->buf, ctx.ctx_id, ctx.cbuf->cdw); in START_TEST()
779 ret = virgl_renderer_submit_cmd(ctx.cbuf->buf, ctx.ctx_id, ctx.cbuf->cdw); in START_TEST()
812 ret = virgl_renderer_submit_cmd(ctx.cbuf->buf, ctx.ctx_id, ctx.cbuf->cdw); in START_TEST()
847 ret = virgl_renderer_submit_cmd(ctx.cbuf->buf, ctx.ctx_id, ctx.cbuf->cdw); in START_TEST()
881 ret = virgl_renderer_submit_cmd(ctx.cbuf->buf, ctx.ctx_id, ctx.cbuf->cdw); in START_TEST()
915 ret = virgl_renderer_submit_cmd(ctx.cbuf->buf, ctx.ctx_id, ctx.cbuf->cdw); in START_TEST()
946 ret = virgl_renderer_submit_cmd(ctx.cbuf->buf, ctx.ctx_id, ctx.cbuf->cdw); in START_TEST()
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| D | testvirgl.h | 36 unsigned cdw; member
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| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_cs.c | 370 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
376 uint64_t ib_dws = MAX2(cs->base.cdw + min_size, in radv_amdgpu_cs_grow()
390 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
396 cs->old_cs_buffers[cs->num_old_cs_buffers].cdw = cs->base.cdw; in radv_amdgpu_cs_grow()
402 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
406 ib_dws = MAX2(cs->base.cdw + min_size, in radv_amdgpu_cs_grow()
422 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
432 while (!cs->base.cdw || (cs->base.cdw & 7) != 4) in radv_amdgpu_cs_grow()
435 *cs->ib_size_ptr |= cs->base.cdw + 4; in radv_amdgpu_cs_grow()
462 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
[all …]
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_cs.h | 134 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_config_reg_seq()
148 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_context_reg_seq()
164 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_context_reg_idx()
173 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_sh_reg_seq()
187 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_uconfig_reg_seq()
203 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_uconfig_reg_idx()
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| D | radeon_vce.h | 39 #define RVCE_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
41 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
46 #define RVCE_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; }
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_build_pm4.h | 46 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_config_reg_seq()
61 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_context_reg_seq()
84 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_context_reg_idx()
94 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_sh_reg_seq()
109 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_uconfig_reg_seq()
125 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_uconfig_reg_idx()
141 assert(cs->current.cdw + 4 <= cs->current.max_dw); in radeon_set_context_reg_rmw()
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| D | si_debug.c | 53 saved->num_dw = cs->prev_dw + cs->current.cdw; in si_save_cs()
60 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4); in si_save_cs()
61 buf += cs->prev[i].cdw; in si_save_cs()
63 memcpy(buf, cs->current.buf, cs->current.cdw * 4); in si_save_cs()
370 if (begin < chunk->cdw) { in si_parse_current_ib()
371 ac_parse_ib_chunk(f, chunk->buf + begin, MIN2(end, chunk->cdw) - begin, last_trace_id, in si_parse_current_ib()
375 if (end <= chunk->cdw) in si_parse_current_ib()
378 if (begin < chunk->cdw) in si_parse_current_ib()
381 begin -= MIN2(begin, chunk->cdw); in si_parse_current_ib()
382 end -= chunk->cdw; in si_parse_current_ib()
[all …]
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| D | si_state_binning.c | 407 unsigned initial_cdw = sctx->gfx_cs->current.cdw; in si_emit_dpbb_disable()
444 if (initial_cdw != sctx->gfx_cs->current.cdw) in si_emit_dpbb_disable()
529 unsigned initial_cdw = sctx->gfx_cs->current.cdw; in si_emit_dpbb_state()
549 if (initial_cdw != sctx->gfx_cs->current.cdw) in si_emit_dpbb_state()
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| /external/mesa3d/src/gallium/drivers/virgl/ |
| D | virgl_encode.h | 60 state->buf[state->cdw++] = dword; in virgl_encoder_write_dword()
66 memcpy(state->buf + state->cdw, &qword, sizeof(uint64_t)); in virgl_encoder_write_qword()
67 state->cdw += 2; in virgl_encoder_write_qword()
74 memcpy(state->buf + state->cdw, ptr, len); in virgl_encoder_write_block()
77 uint8_t *mp = (uint8_t *)(state->buf + state->cdw); in virgl_encoder_write_block()
81 state->cdw += (len + 3) / 4; in virgl_encoder_write_block()
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| D | virgl_transfer_queue.c | 329 uint32_t prior_num_dwords = cbuf->cdw; in virgl_transfer_queue_clear()
330 cbuf->cdw = 0; in virgl_transfer_queue_clear()
337 cbuf->cdw = prior_num_dwords; in virgl_transfer_queue_clear()
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| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_cs.c | 789 ib->base.current.cdw = 0; in amdgpu_get_new_ib()
820 *ib->ptr_ib_size = ib->base.current.cdw | in amdgpu_set_ib_size()
823 *ib->ptr_ib_size = ib->base.current.cdw; in amdgpu_set_ib_size()
830 ib->used_ib_space += ib->base.current.cdw * 4; in amdgpu_ib_finalize()
832 ib->max_ib_size = MAX2(ib->max_ib_size, ib->base.prev_dw + ib->base.current.cdw); in amdgpu_ib_finalize()
1098 unsigned requested_size = rcs->prev_dw + rcs->current.cdw + dw; in amdgpu_cs_check_space()
1104 assert(rcs->current.cdw <= rcs->current.max_dw); in amdgpu_cs_check_space()
1118 if (rcs->current.max_dw - rcs->current.cdw >= dw) in amdgpu_cs_check_space()
1153 while ((rcs->current.cdw & ib_pad_dw_mask) != ib_pad_dw_mask - 3) in amdgpu_cs_check_space()
1159 new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw++]; in amdgpu_cs_check_space()
[all …]
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| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_cs.c | 435 assert(cs->base.current.cdw == 0); in radeon_drm_cs_validate()
436 if (cs->base.current.cdw != 0) { in radeon_drm_cs_validate()
447 assert(rcs->current.cdw <= rcs->current.max_dw); in radeon_drm_cs_check_space()
448 return rcs->current.max_dw - rcs->current.cdw >= dw; in radeon_drm_cs_check_space()
574 while (rcs->current.cdw & 7) in radeon_drm_cs_flush()
577 while (rcs->current.cdw & 7) in radeon_drm_cs_flush()
586 while (rcs->current.cdw & 7) in radeon_drm_cs_flush()
589 while (rcs->current.cdw & 7) in radeon_drm_cs_flush()
594 while (rcs->current.cdw & 15) in radeon_drm_cs_flush()
601 if (rcs->current.cdw > rcs->current.max_dw) { in radeon_drm_cs_flush()
[all …]
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | radeon_common.c | 427 if (radeon->cmdbuf.cs->cdw && !radeon->hw.all_dirty) { in radeonCountStateEmitSize()
505 if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) in radeonEmitState()
508 if (!radeon->cmdbuf.cs->cdw) { in radeonEmitState()
530 fprintf(stderr, "%s %d\n", __func__, radeon->cmdbuf.cs->cdw); in radeonFlush()
537 if (!radeon->dma.flush && !radeon->cmdbuf.cs->cdw && is_empty_list(&radeon->dma.reserved)) in radeonFlush()
543 if (radeon->cmdbuf.cs->cdw) in radeonFlush()
608 if (rmesa->cmdbuf.cs->cdw) { in rcommonFlushCmdBufLocked()
647 if ((rmesa->cmdbuf.cs->cdw + dwords + 128) > rmesa->cmdbuf.size in rcommonEnsureCmdBufSpace()
650 assert(rmesa->cmdbuf.cs->cdw); in rcommonEnsureCmdBufSpace()
719 n, rmesa->cmdbuf.cs->cdw, function, line); in rcommonBeginBatch()
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_common.c | 427 if (radeon->cmdbuf.cs->cdw && !radeon->hw.all_dirty) { in radeonCountStateEmitSize()
505 if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) in radeonEmitState()
508 if (!radeon->cmdbuf.cs->cdw) { in radeonEmitState()
530 fprintf(stderr, "%s %d\n", __func__, radeon->cmdbuf.cs->cdw); in radeonFlush()
537 if (!radeon->dma.flush && !radeon->cmdbuf.cs->cdw && is_empty_list(&radeon->dma.reserved)) in radeonFlush()
543 if (radeon->cmdbuf.cs->cdw) in radeonFlush()
608 if (rmesa->cmdbuf.cs->cdw) { in rcommonFlushCmdBufLocked()
647 if ((rmesa->cmdbuf.cs->cdw + dwords + 128) > rmesa->cmdbuf.size in rcommonEnsureCmdBufSpace()
650 assert(rmesa->cmdbuf.cs->cdw); in rcommonEnsureCmdBufSpace()
719 n, rmesa->cmdbuf.cs->cdw, function, line); in rcommonBeginBatch()
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| D | radeon_tcl.c | 400 + rmesa->radeon.cmdbuf.cs->cdw; in radeon_run_tcl_render()
420 if (emit_end < rmesa->radeon.cmdbuf.cs->cdw) in radeon_run_tcl_render()
422 " We might overflow command buffer.\n", rmesa->radeon.cmdbuf.cs->cdw - emit_end); in radeon_run_tcl_render()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_winsys.h | 193 unsigned cdw; /* Number of used dwords. */ member
708 return cs && (cs->prev_dw + cs->current.cdw > num_dw); in radeon_emitted()
713 cs->current.buf[cs->current.cdw++] = value; in radeon_emit()
719 memcpy(cs->current.buf + cs->current.cdw, values, count * 4); in radeon_emit_array()
720 cs->current.cdw += count; in radeon_emit_array()
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| D | radeon_uvd_enc_1_1.c | 38 #define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
41 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
50 *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
79 enc->cs->current.buf[enc->cs->current.cdw] = 0; in radeon_uvd_enc_output_one_byte()
80 enc->cs->current.buf[enc->cs->current.cdw] |= in radeon_uvd_enc_output_one_byte()
86 enc->cs->current.cdw++; in radeon_uvd_enc_output_one_byte()
162 enc->cs->current.cdw++; in radeon_uvd_enc_flush_headers()
214 enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_uvd_enc_task_info()
394 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_uvd_enc_nalu_sps_hevc()
489 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_uvd_enc_nalu_pps_hevc()
[all …]
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| D | radeon_vce.h | 34 #define RVCE_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
37 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
46 *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
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