/external/mesa3d/src/amd/common/ |
D | ac_debug.c | 61 enum chip_class chip_class; member 101 static const struct si_reg *find_register(enum chip_class chip_class, unsigned offset) in find_register() argument 106 switch (chip_class) { in find_register() 142 const char *ac_get_register_name(enum chip_class chip_class, unsigned offset) in ac_get_register_name() argument 144 const struct si_reg *reg = find_register(chip_class, offset); in ac_get_register_name() 149 void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset, uint32_t value, in ac_dump_reg() argument 152 const struct si_reg *reg = find_register(chip_class, offset); in ac_dump_reg() 235 ac_dump_reg(f, ib->chip_class, reg + i * 4, ac_ib_get(ib), ~0); in ac_parse_set_reg_packet() 279 ac_dump_reg(f, ib->chip_class, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0); in ac_parse_packet3() 280 ac_dump_reg(f, ib->chip_class, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0); in ac_parse_packet3() [all …]
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D | ac_debug.h | 59 const char *ac_get_register_name(enum chip_class chip_class, unsigned offset); 60 void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset, uint32_t value, 63 unsigned trace_id_count, enum chip_class chip_class, 66 const char *name, enum chip_class chip_class, ac_debug_addr_callback addr_callback, 69 bool ac_vm_fault_occured(enum chip_class chip_class, uint64_t *old_dmesg_timestamp, 72 unsigned ac_get_wave_info(enum chip_class chip_class,
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D | ac_shader_util.h | 85 uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class); 87 unsigned ac_get_tbuffer_format(enum chip_class chip_class, unsigned dfmt, unsigned nfmt); 91 enum ac_image_dim ac_get_sampler_dim(enum chip_class chip_class, enum glsl_sampler_dim dim, 94 enum ac_image_dim ac_get_image_dim(enum chip_class chip_class, enum glsl_sampler_dim sdim,
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D | ac_shadowed_regs.c | 819 void ac_get_reg_ranges(enum chip_class chip_class, enum radeon_family family, in ac_get_reg_ranges() argument 834 if (chip_class == GFX10_3) in ac_get_reg_ranges() 836 else if (chip_class == GFX10) in ac_get_reg_ranges() 838 else if (chip_class == GFX9) in ac_get_reg_ranges() 842 if (chip_class == GFX10_3) in ac_get_reg_ranges() 844 else if (chip_class == GFX10) in ac_get_reg_ranges() 846 else if (chip_class == GFX9) in ac_get_reg_ranges() 850 if (chip_class == GFX10_3 || chip_class == GFX10) in ac_get_reg_ranges() 854 else if (chip_class == GFX9) in ac_get_reg_ranges() 858 if (chip_class == GFX10_3 || chip_class == GFX10) in ac_get_reg_ranges() [all …]
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D | ac_shader_util.c | 86 uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class) in ac_vgt_gs_mode() argument 102 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= GFX8) | S_028A40_GS_WRITE_OPTIMIZE(1) | in ac_vgt_gs_mode() 103 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0); in ac_vgt_gs_mode() 108 unsigned ac_get_tbuffer_format(enum chip_class chip_class, unsigned dfmt, unsigned nfmt) in ac_get_tbuffer_format() argument 115 if (chip_class >= GFX10) { in ac_get_tbuffer_format() 218 enum ac_image_dim ac_get_sampler_dim(enum chip_class chip_class, enum glsl_sampler_dim dim, in ac_get_sampler_dim() argument 223 if (chip_class == GFX9) in ac_get_sampler_dim() 245 enum ac_image_dim ac_get_image_dim(enum chip_class chip_class, enum glsl_sampler_dim sdim, in ac_get_image_dim() argument 248 enum ac_image_dim dim = ac_get_sampler_dim(chip_class, sdim, is_array); in ac_get_image_dim() 251 if (dim == ac_image_cube || (chip_class <= GFX8 && dim == ac_image_3d)) in ac_get_image_dim() [all …]
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D | ac_gpu_info.c | 160 if (info->chip_class < GFX9) in has_tmz_support() 452 info->chip_class = GFX10_3; in ac_query_gpu_info() 454 info->chip_class = GFX10; in ac_query_gpu_info() 456 info->chip_class = GFX9; in ac_query_gpu_info() 458 info->chip_class = GFX8; in ac_query_gpu_info() 460 info->chip_class = GFX7; in ac_query_gpu_info() 462 info->chip_class = GFX6; in ac_query_gpu_info() 494 info->has_l2_uncached = info->chip_class >= GFX9; in ac_query_gpu_info() 525 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 || info->drm_minor >= 2; in ac_query_gpu_info() 528 info->has_unaligned_shader_loads = info->chip_class != GFX6; in ac_query_gpu_info() [all …]
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D | ac_shadowed_regs.h | 53 void ac_get_reg_ranges(enum chip_class chip_class, enum radeon_family family, 58 void ac_check_shadowed_regs(enum chip_class chip_class, enum radeon_family family,
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/external/mesa3d/src/amd/vulkan/winsys/null/ |
D | radv_null_winsys.c | 77 info->chip_class = CLASS_UNKNOWN; in radv_null_winsys_query_info() 87 info->chip_class = GFX10_3; in radv_null_winsys_query_info() 89 info->chip_class = GFX10; in radv_null_winsys_query_info() 91 info->chip_class = GFX9; in radv_null_winsys_query_info() 93 info->chip_class = GFX8; in radv_null_winsys_query_info() 95 info->chip_class = GFX7; in radv_null_winsys_query_info() 97 info->chip_class = GFX6; in radv_null_winsys_query_info() 110 if (info->chip_class >= GFX10_3) in radv_null_winsys_query_info() 112 else if (info->chip_class >= GFX10) in radv_null_winsys_query_info() 119 if (info->chip_class >= GFX10) in radv_null_winsys_query_info() [all …]
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/external/mesa3d/src/amd/compiler/ |
D | aco_assembler.cpp | 15 enum chip_class chip_class; member 21 asm_context(Program* program) : program(program), chip_class(program->chip_class) { in asm_context() 22 if (chip_class <= GFX7) in asm_context() 24 else if (chip_class <= GFX9) in asm_context() 26 else if (chip_class >= GFX10) in asm_context() 55 if (opcode >= 55 && ctx.chip_class <= GFX9) { in emit_instruction() 56 assert(ctx.chip_class == GFX9 && opcode < 60); in emit_instruction() 115 assert(ctx.chip_class >= GFX10); in emit_instruction() 119 assert(ctx.chip_class >= GFX10); in emit_instruction() 141 if (opcode >= 55 && ctx.chip_class <= GFX9) { in emit_instruction() [all …]
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D | aco_ir.cpp | 62 enum chip_class chip_class, enum radeon_family family, in init_program() argument 68 program->chip_class = chip_class; in init_program() 70 switch (chip_class) { in init_program() 96 program->lds_alloc_granule = chip_class >= GFX7 ? 512 : 256; in init_program() 97 program->lds_limit = chip_class >= GFX7 ? 65536 : 32768; in init_program() 104 if (chip_class >= GFX10) { in init_program() 108 if (chip_class >= GFX10_3) in init_program() 112 } else if (program->chip_class >= GFX8) { in init_program() 159 bool can_use_SDWA(chip_class chip, const aco_ptr<Instruction>& instr) in can_use_SDWA() 222 aco_ptr<Instruction> convert_to_SDWA(chip_class chip, aco_ptr<Instruction>& instr) in convert_to_SDWA() [all …]
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D | aco_insert_waitcnt.cpp | 138 wait_imm(enum chip_class chip, uint16_t packed) : vs(unset_counter) in wait_imm() 151 uint16_t pack(enum chip_class chip) const in pack() 261 enum chip_class chip_class; member 291 chip_class(program_->chip_class), in wait_ctx() 292 max_vm_cnt(program_->chip_class >= GFX9 ? 62 : 14), in wait_ctx() 294 max_lgkm_cnt(program_->chip_class >= GFX10 ? 62 : 14), in wait_ctx() 295 max_vs_cnt(program_->chip_class >= GFX10 ? 62 : 0), in wait_ctx() 296 unordered_events(event_smem | (program_->chip_class < GFX10 ? event_flat : 0)), in wait_ctx() 445 return wait_imm(ctx.chip_class, static_cast<SOPP_instruction*>(instr)->imm); in parse_wait_instr() 467 if (ctx.chip_class < GFX10 && sync.scope <= scope_workgroup) in perform_barrier() [all …]
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/external/mesa3d/src/amd/vulkan/ |
D | radv_debug.c | 79 ac_vm_fault_occured(device->physical_device->rad_info.chip_class, in radv_init_trace() 99 ac_dump_reg(f, device->physical_device->rad_info.chip_class, in radv_dump_mmapped_reg() 124 if (info->chip_class <= GFX8) { in radv_dump_debug_registers() 143 radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc, in radv_dump_buffer_descriptor() argument 148 ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, in radv_dump_buffer_descriptor() 153 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc, in radv_dump_image_descriptor() argument 156 unsigned sq_img_rsrc_word0 = chip_class >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0 in radv_dump_image_descriptor() 161 ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4, in radv_dump_image_descriptor() 166 ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4, in radv_dump_image_descriptor() 171 radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc, in radv_dump_sampler_descriptor() argument [all …]
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D | si_cmd_buffer.c | 53 if (physical_device->rad_info.chip_class < GFX7) in si_write_harvested_raster_configs() 66 if (physical_device->rad_info.chip_class < GFX7) in si_write_harvested_raster_configs() 76 if (physical_device->rad_info.chip_class >= GFX7) in si_write_harvested_raster_configs() 95 if (device->physical_device->rad_info.chip_class >= GFX7) { in si_emit_compute() 113 if (device->physical_device->rad_info.chip_class >= GFX9) { in si_emit_compute() 115 device->physical_device->rad_info.chip_class >= GFX10 ? 0x20 : 0); in si_emit_compute() 118 if (device->physical_device->rad_info.chip_class >= GFX10) { in si_emit_compute() 132 if (device->physical_device->rad_info.chip_class <= GFX6) { in si_emit_compute() 171 if (physical_device->rad_info.chip_class >= GFX7) in si_set_raster_config() 199 if (physical_device->rad_info.chip_class <= GFX8) in si_emit_graphics() [all …]
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D | radv_sqtt.c | 72 assert(device->physical_device->rad_info.chip_class >= GFX8); in radv_emit_thread_trace_start() 84 if (device->physical_device->rad_info.chip_class == GFX10) { in radv_emit_thread_trace_start() 142 if (device->physical_device->rad_info.chip_class < GFX9) { in radv_emit_thread_trace_start() 166 if (device->physical_device->rad_info.chip_class == GFX9) { in radv_emit_thread_trace_start() 183 if (device->physical_device->rad_info.chip_class == GFX9) { in radv_emit_thread_trace_start() 201 device->physical_device->rad_info.chip_class >= GFX7) { in radv_emit_thread_trace_start() 238 switch (device->physical_device->rad_info.chip_class) { in radv_copy_thread_trace_info_regs() 275 assert(device->physical_device->rad_info.chip_class >= GFX8); in radv_emit_thread_trace_stop() 279 device->physical_device->rad_info.chip_class >= GFX7) { in radv_emit_thread_trace_stop() 297 if (device->physical_device->rad_info.chip_class == GFX10) { in radv_emit_thread_trace_stop() [all …]
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D | radv_shader.c | 570 if (device->physical_device->rad_info.chip_class == GFX6) { in radv_shader_compile_to_nir() 622 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7; in radv_shader_compile_to_nir() 683 if (ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class) && in radv_shader_compile_to_nir() 884 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0) in radv_postprocess_config() 885 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0)); in radv_postprocess_config() 918 if (pdevice->rad_info.chip_class >= GFX10) { in radv_postprocess_config() 928 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config() 932 assert(pdevice->rad_info.chip_class <= GFX8); in radv_postprocess_config() 941 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config() 948 if (pdevice->rad_info.chip_class >= GFX9) { in radv_postprocess_config() [all …]
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D | radv_shader.h | 148 enum chip_class chip_class; member 488 radv_get_max_workgroup_size(enum chip_class chip_class, 511 calculate_tess_lds_size(enum chip_class chip_class, in calculate_tess_lds_size() argument 531 if (chip_class >= GFX7) { in calculate_tess_lds_size() 549 enum chip_class chip_class, in get_tcs_num_patches() argument 573 if (chip_class >= GFX7 && family != CHIP_STONEY) in get_tcs_num_patches() 587 if (chip_class == GFX6) { in get_tcs_num_patches()
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/external/mesa3d/src/amd/compiler/tests/ |
D | test_assembler.cpp | 30 if (!setup_cs(NULL, (chip_class)i)) 44 if (!setup_cs(NULL, (chip_class)GFX10)) 63 if (!setup_cs(NULL, (chip_class)GFX10)) 93 if (!setup_cs(NULL, (chip_class)GFX10)) 126 if (!setup_cs(NULL, (chip_class)GFX10)) 154 if (!setup_cs(NULL, (chip_class)GFX10)) 183 if (!setup_cs(NULL, (chip_class)GFX10)) 208 if (!setup_cs(NULL, (chip_class)GFX10)) 233 if (!setup_cs(NULL, (chip_class)i)) 251 if (!setup_cs(NULL, (chip_class)i))
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D | helpers.h | 71 void create_program(enum chip_class chip_class, aco::Stage stage, 73 bool setup_cs(const char *input_spec, enum chip_class chip_class, 85 VkDevice get_vk_device(enum chip_class chip_class);
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/external/mesa3d/src/gallium/winsys/radeon/drm/ |
D | radeon_drm_winsys.c | 216 ws->info.chip_class = R300; in do_winsys_init() 227 ws->info.chip_class = R400; in do_winsys_init() 235 ws->info.chip_class = R500; in do_winsys_init() 245 ws->info.chip_class = R600; in do_winsys_init() 251 ws->info.chip_class = R700; in do_winsys_init() 264 ws->info.chip_class = EVERGREEN; in do_winsys_init() 268 ws->info.chip_class = CAYMAN; in do_winsys_init() 275 ws->info.chip_class = GFX6; in do_winsys_init() 281 ws->info.chip_class = GFX7; in do_winsys_init() 312 if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) { in do_winsys_init() [all …]
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/external/mesa3d/src/gallium/drivers/radeonsi/ |
D | si_pipe.c | 144 !sscreen->info.has_dedicated_vram && sscreen->info.chip_class <= GFX8; in si_init_compiler() 148 (sscreen->info.chip_class <= GFX8 ? AC_TM_FORCE_DISABLE_XNACK : in si_init_compiler() 149 sscreen->info.chip_class <= GFX10 ? AC_TM_FORCE_ENABLE_XNACK : 0) | in si_init_compiler() 186 if (sctx->chip_class >= GFX10 && sctx->has_graphics) in si_destroy_context() 451 sctx->has_graphics = sscreen->info.chip_class == GFX6 || !(flags & PIPE_CONTEXT_COMPUTE_ONLY); in si_create_context() 467 sctx->chip_class = sscreen->info.chip_class; in si_create_context() 469 if (sctx->chip_class == GFX7 || sctx->chip_class == GFX8 || sctx->chip_class == GFX9) { in si_create_context() 553 if (sctx->chip_class >= GFX10) in si_create_context() 580 if (sctx->chip_class >= GFX10) in si_create_context() 615 if (sctx->chip_class >= GFX7) in si_create_context() [all …]
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D | si_state.c | 102 if (sctx->chip_class >= GFX8) { in si_emit_cb_render_state() 113 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) | in si_emit_cb_render_state() 581 if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10) in si_create_blend_state_mode() 592 if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10 && logicop_enable) in si_create_blend_state_mode() 754 S_02881C_BYPASS_VTX_RATE_COMBINER(sctx->chip_class >= GFX10_3) | in si_emit_clip_regs() 755 S_02881C_BYPASS_PRIM_RATE_COMBINER(sctx->chip_class >= GFX10_3) | in si_emit_clip_regs() 758 if (sctx->chip_class >= GFX10) { in si_emit_clip_regs() 915 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9)); in si_create_rs_state() 930 … S_028814_KEEP_TOGETHER_ENABLE(sscreen->info.chip_class >= GFX10 ? rs->polygon_mode_enabled : 0)); in si_create_rs_state() 1363 bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect; in si_emit_db_render_state() [all …]
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D | si_state_draw.c | 79 bool has_primid_instancing_bug = sctx->chip_class == GFX6 && sctx->screen->info.max_se == 1; in si_emit_derived_tess_state() 91 if (sctx->chip_class >= GFX9) { in si_emit_derived_tess_state() 182 if (sctx->chip_class == GFX6) { in si_emit_derived_tess_state() 232 if (sctx->chip_class >= GFX7) { in si_emit_derived_tess_state() 249 if (sctx->chip_class >= GFX9) { in si_emit_derived_tess_state() 252 if (sctx->chip_class >= GFX10) in si_emit_derived_tess_state() 273 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII) in si_emit_derived_tess_state() 297 if (sctx->chip_class >= GFX7) { in si_emit_derived_tess_state() 348 if (sscreen->info.chip_class == GFX8) in si_get_init_multi_vgt_param() 362 if (sscreen->info.chip_class >= GFX7) { in si_get_init_multi_vgt_param() [all …]
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D | si_debug.c | 300 ac_dump_reg(f, sctx->chip_class, offset, value, ~0); in si_dump_mmapped_reg() 324 if (sctx->chip_class <= GFX8) { in si_dump_debug_registers() 359 enum chip_class chip_class) in si_parse_current_ib() argument 372 trace_id_count, chip_class, NULL, NULL); in si_parse_current_ib() 388 chip_class, NULL, NULL); in si_parse_current_ib() 416 "IB2: Init config", ctx->chip_class, NULL, NULL); in si_log_chunk_type_cs_print() 420 "IB2: Init GS rings", ctx->chip_class, NULL, NULL); in si_log_chunk_type_cs_print() 425 &last_trace_id, map ? 1 : 0, "IB", ctx->chip_class, NULL, NULL); in si_log_chunk_type_cs_print() 428 map ? 1 : 0, "IB", ctx->chip_class); in si_log_chunk_type_cs_print() 438 "Compute IB", ctx->chip_class, NULL, NULL); in si_log_chunk_type_cs_print() [all …]
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/external/mesa3d/src/gallium/drivers/r600/sfn/ |
D | sfn_nir.h | 60 r600_shader *gs_shader, enum chip_class chip_class); 82 enum chip_class chip_class; variable
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/external/mesa3d/src/gallium/drivers/r600/ |
D | r600_hw_context.c | 76 if (ctx->b.chip_class == R600) { in r600_need_cs_space() 142 if (rctx->b.chip_class >= R700 && in r600_flush_emit() 148 if (rctx->b.chip_class >= R700 && in r600_flush_emit() 163 (rctx->b.chip_class == R600 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)) { in r600_flush_emit() 189 if (rctx->b.chip_class >= R700 && in r600_flush_emit() 199 if (rctx->b.chip_class >= R700 && in r600_flush_emit() 211 if (rctx->b.chip_class >= EVERGREEN) in r600_flush_emit() 218 if (rctx->b.chip_class >= R700 && in r600_flush_emit() 288 if (ctx->b.chip_class == R600) { in r600_context_gfx_flush() 359 if (ctx->b.chip_class >= EVERGREEN) { in r600_begin_new_cs() [all …]
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