| /external/mesa3d/src/amd/registers/ |
| D | makeregheader.py | 63 def get_disambiguation_suffix(chips): argument
68 oldest_chip_index = min([get_chip_index(chip) for chip in chips])
71 def get_chips_comment(chips, parent=None): argument
83 chipflags = [chip.name in chips for chip in CHIPS]
132 chips=set(regmap.chips),
140 if type_ref is not None and regtype_emit[key].isdisjoint(regmap.chips):
141 regtype_emit[key].update(regmap.chips)
151 chips=set(regmap.chips),
160 if enum_ref is not None and enum_emit[key].isdisjoint(regmap.chips):
161 enum_emit[key].update(regmap.chips)
[all …]
|
| D | regdb.py | 241 chips = set(getattr(regmap, 'chips', ['undef']))
244 self.__chips.update(chips)
257 other.chips = sorted(list(chips.union(other_chips)))
272 type_ref != other_type_ref and chips.intersection(other_chips):
539 def chips(self): member in RegisterDatabase
546 def merge_chips(self, chips, newchip): argument
553 chips = set(chips)
562 if chips.isdisjoint(regmap.chips):
568 if chips.isdisjoint(other.chips):
664 regmap_accum.chips = [newchip]
[all …]
|
| D | canonicalize.py | 71 def json_canonicalize(filp, chips = None): argument
74 if chips is not None:
77 regmap.chips = [chips]
|
| D | parseheader.py | 51 self.chips = ['gfx6', 'gfx7', 'gfx8', 'fiji', 'stoney', 'gfx9']
84 chips = ['gfx6', 'gfx7', 'gfx8', 'fiji', 'stoney', 'gfx9']
176 chips=self.chips,
|
| /external/llvm/test/CodeGen/X86/ |
| D | slow-unaligned-mem.ll | 1 ; Intel chips with slow unaligned memory accesses
15 ; Intel chips with fast unaligned memory accesses
27 ; AMD chips with slow unaligned memory accesses
39 ; AMD chips with fast unaligned memory accesses
50 ; Other chips with slow unaligned memory accesses
55 ; Slow chips use 4-byte stores. Fast chips with SSE or later use something other than 4-byte stores.
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | slow-unaligned-mem.ll | 1 ; Intel chips with slow unaligned memory accesses
15 ; Intel chips with fast unaligned memory accesses
27 ; AMD chips with slow unaligned memory accesses
39 ; AMD chips with fast unaligned memory accesses
52 ; Other chips with slow unaligned memory accesses
57 ; Slow chips use 4-byte stores. Fast chips with SSE or later use something other than 4-byte stores.
|
| /external/python/cpython2/Tools/pynche/ |
| D | StripViewer.py | 207 chips = self.__chips = []
218 chips.append(color)
230 chipx = self.__arrow_x(len(chips) - 1)
295 chips = self.__chips = []
300 chips.append(rrggbb)
306 colors = SPACE.join(chips)
|
| /external/python/cpython3/Tools/pynche/ |
| D | StripViewer.py | 207 chips = self.__chips = []
218 chips.append(color)
230 chipx = self.__arrow_x(len(chips) - 1)
295 chips = self.__chips = []
300 chips.append(rrggbb)
306 colors = SPACE.join(chips)
|
| /external/crosvm/devices/src/irqchip/kvm/ |
| D | x86_64.rs | 227 let mut chips = Vec::new(); in routes_to_chips() localVariable
236 | IrqSourceChip::Ioapic => chips.push((*chip, *pin)), in routes_to_chips()
245 chips in routes_to_chips()
401 let chips = self.routes_to_chips(irq); in service_irq() localVariable
402 for (chip, pin) in chips { in service_irq()
427 let chips = self.routes_to_chips(evt.gsi); in service_irq_event() localVariable
429 for (chip, pin) in chips { in service_irq_event()
|
| /external/tensorflow/tensorflow/lite/tools/make/targets/ |
| D | aarch64_makefile.inc | 3 # The aarch64 architecture covers all 64-bit ARM chips. This arch mandates
|
| /external/autotest/client/site_tests/hardware_LightSensor/ |
| D | control | 21 light-to-digital converters (ie, light sensor chips).
|
| /external/mesa3d/docs/ |
| D | developers.rst | 12 - DRI drivers for Intel i965, i945, i915 and other chips
|
| /external/tensorflow/tensorflow/core/protobuf/tpu/ |
| D | topology.proto | 10 // topology [x, y, core], where the major dimensions correspond to TPU chips,
|
| /external/autotest/server/site_tests/firmware_CorruptRecoveryCache/ |
| D | control | 21 cache and boots into recovery. This only applies to intel chips.
|
| D | control.dev | 21 cache and boots into recovery. This only applies to intel chips.
|
| /external/mesa3d/docs/relnotes/ |
| D | 19.2.1.rst | 124 - ac: fix num_good_cu_per_sh for harvested chips
126 - radeonsi/gfx10: fix corruption for chips with harvested TCCs
|
| D | 7.0.2.rst | 35 - Added checking/support for additional chips in the i915/i945 family
|
| /external/tensorflow/tensorflow/core/profiler/protobuf/ |
| D | op_stats.proto | 48 // System topology, which describes the number of chips in a pod
56 // The number of expected bad chips in this system.
|
| /external/pigweed/pw_sys_io_baremetal_stm32f429/ |
| D | docs.rst | 15 all STM32F429 variations (and even some STM32F4xx chips).
|
| /external/rust/crates/libz-sys/src/zlib/contrib/asm686/ |
| D | README.686 | 43 in it. On the Pentium 4 and AMD64 chips, it continues to run about 8%
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | README-FPStack.txt | 12 This should use fiadd on chips where it is profitable:
|
| /external/llvm/lib/Target/X86/ |
| D | README-FPStack.txt | 12 This should use fiadd on chips where it is profitable:
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | README-FPStack.txt | 12 This should use fiadd on chips where it is profitable:
|
| /external/llvm/docs/ |
| D | CompilerWriterInfo.rst | 49 * `PowerPC Compiler Writer's Guide <http://www.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20…
53 * `PowerPC Processor Manuals (embedded) <http://www.ibm.com/chips/techlib/techlib.nsf/products/Powe…
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.SI.fs.interp.ll | 23 ; on 16 bank LDS chips.
|