csinc (reference) in projects: external

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Searched refs:csinc (Results 1 – 25 of 60) sorted by relevance

12 3

/external/llvm-project/llvm/test/CodeGen/AArch64/
D	use-cr-result-of-dom-icmp-st.ll	`27 ; CHECK-NEXT: csinc x8, x1, xzr, ge 55 ; CHECK-NEXT: csinc x8, x1, xzr, ge 83 ; CHECK-NEXT: csinc x8, x1, xzr, ge 111 ; CHECK-NEXT: csinc x8, x1, xzr, ge 139 ; CHECK-NEXT: csinc x8, x1, xzr, ge 166 ; CHECK-NEXT: csinc x8, x1, xzr, ge 192 ; CHECK-NEXT: csinc x8, x1, xzr, ge 218 ; CHECK-NEXT: csinc x8, x1, xzr, ge 244 ; CHECK-NEXT: csinc x8, x1, xzr, ge 270 ; CHECK-NEXT: csinc x8, x1, xzr, ge [all …]`
D	cond-sel-value-prop.ll	`54 ; CHECK: csinc x0, x[[REG]], xzr, ne 76 ; CHECK: csinc x0, x[[REG]], xzr, eq 85 ; CHECK: csinc x0, x[[REG]], xzr, eq`
D	sve-extract-vector.ll	`28 ; CHECK-NEXT: csinc x8, x8, xzr, lo 60 ; CHECK-NEXT: csinc x8, x8, xzr, lo 92 ; CHECK-NEXT: csinc x8, x8, xzr, lo 125 ; CHECK-NEXT: csinc x8, x8, xzr, lo`
D	cond-sel.ll	`67 ; CHECK: csinc {{w[0-9]+}}, [[LHS]], [[RHS]], ls 75 ; CHECK: csinc {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le 84 ; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls 92 ; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le 209 ; N.b. code is not optimal here (32-bit csinc would be better) but`
D	sve-insert-vector.ll	`37 ; CHECK-NEXT: csinc x8, x8, xzr, lo 81 ; CHECK-NEXT: csinc x8, x8, xzr, lo 125 ; CHECK-NEXT: csinc x8, x8, xzr, lo 169 ; CHECK-NEXT: csinc x8, x8, xzr, lo`
D	arm64-csel.ll	`237 ; CHECK: csinc w0, w[[REG]], wzr, eq 247 ; CHECK: csinc x0, x[[REG]], xzr, eq 257 ; CHECK: csinc w0, w[[REG]], wzr, ne 267 ; CHECK: csinc x0, x[[REG]], xzr, ne`
D	arm64-fast-isel-fcmp.ll	`87 ; CHECK-NEXT: csinc {{w[0-9]+}}, [[REG]], wzr, le 112 ; CHECK-NEXT: csinc {{w[0-9]+}}, [[REG]], wzr, vc`
D	ssub_sat_vec.ll	`379 ; CHECK-NEXT: csinc w9, w9, wzr, ne 382 ; CHECK-NEXT: csinc w10, w10, wzr, ne 390 ; CHECK-NEXT: csinc w13, w13, wzr, ne 400 ; CHECK-NEXT: csinc w9, w9, wzr, ne 403 ; CHECK-NEXT: csinc w10, w10, wzr, ne 410 ; CHECK-NEXT: csinc w13, w13, wzr, ne`
D	sadd_sat_vec.ll	`378 ; CHECK-NEXT: csinc w9, w9, wzr, ne 381 ; CHECK-NEXT: csinc w10, w10, wzr, ne 389 ; CHECK-NEXT: csinc w13, w13, wzr, ne 399 ; CHECK-NEXT: csinc w9, w9, wzr, ne 402 ; CHECK-NEXT: csinc w10, w10, wzr, ne 409 ; CHECK-NEXT: csinc w13, w13, wzr, ne`
D	ifcvt-select.ll	`7 ;CHECK: csinc`
D	arm64-early-ifcvt.ll	`42 ; CHECK-NEXT: csinc w0, w1, w0, eq 60 ; CHECK-NEXT: csinc x0, x1, x0, eq 78 ; CHECK-NEXT: csinc w0, w1, w0, ne 96 ; CHECK-NEXT: csinc x0, x1, x0, ne`
D	half.ll	`114 ; CHECK-NEXT: csinc w9, w9, wzr, mi`
/external/llvm-project/llvm/test/MC/ARM/
D	thumbv8.1m.s	`1068 csinc lr, r2, r2, hs label 1100 # CHECK: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e] 1101 # CHECK-FP: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e] 1102 # CHECK-NOLOB: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e] 1103 csinc lr, r10, r7, le label 1131 csinc r0, sp, r1, eq label 1133 csinc r0, pc, r1, eq label 1156 csinc r0, r0, r1, ne label`
D	mve-scalar-shift.s	`52 csinc lr, r2, r2, hs label 78 # CHECK: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e] 79 # CHECK-NOMVE: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e] 80 csinc lr, r10, r7, le label`
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
D	fold-select.mir	`70 name: csinc 79 ; CHECK-LABEL: name: csinc`
/external/llvm/test/CodeGen/AArch64/
D	cond-sel.ll	`67 ; CHECK: csinc {{w[0-9]+}}, [[LHS]], [[RHS]], ls 75 ; CHECK: csinc {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le 84 ; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls 92 ; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le 209 ; N.b. code is not optimal here (32-bit csinc would be better) but`
D	arm64-fast-isel-fcmp.ll	`87 ; CHECK-NEXT: csinc {{w[0-9]+}}, [[REG]], wzr, le 112 ; CHECK-NEXT: csinc {{w[0-9]+}}, [[REG]], wzr, vc`
D	arm64-early-ifcvt.ll	`42 ; CHECK-NEXT: csinc w0, w1, w0, eq 60 ; CHECK-NEXT: csinc x0, x1, x0, eq 78 ; CHECK-NEXT: csinc w0, w1, w0, ne 96 ; CHECK-NEXT: csinc x0, x1, x0, ne`
D	ifcvt-select.ll	`7 ;CHECK: csinc`
/external/arm-trusted-firmware/plat/rpi/common/aarch64/
D	plat_helpers.S	`212 csinc w0, w0, w0, ne`
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
D	A55-basic-instructions.s	`390 csinc w1, w0, w19, ne label 391 csinc wzr, w5, w9, eq label 392 csinc w9, wzr, w30, gt label 393 csinc w1, w28, wzr, mi label 394 csinc x19, x23, x29, lt label 395 csinc xzr, x3, x4, ge label 396 csinc x5, xzr, x6, hs label 397 csinc x7, x8, xzr, lo label 418 csinc w2, wzr, wzr, al label 426 csinc w5, w6, w6, nv label [all …]`
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
D	thumbv8.1m.s	`26 # CHECK: csinc lr, r10, r7, le @ encoding: [0x5a,0xea,0xd7,0x9e]`
/external/llvm-project/clang/test/Driver/
D	armv8.1m.main.s	`31 csinc r0, r1, r2, eq label`
/external/llvm-project/llvm/test/CodeGen/Thumb2/
D	csel.ll	`122 ; CHECK-NEXT: csinc r0, r1, r2, gt 135 ; CHECK-NEXT: csinc r0, r2, r1, le`
/external/capstone/suite/MC/AArch64/
D	basic-a64-instructions.s.cs	`508 0x01,0x14,0x93,0x1a = csinc w1, w0, w19, ne 509 0xbf,0x04,0x89,0x1a = csinc wzr, w5, w9, eq 510 0xe9,0xc7,0x9e,0x1a = csinc w9, wzr, w30, gt 511 0x81,0x47,0x9f,0x1a = csinc w1, w28, wzr, mi 512 0xf3,0xb6,0x9d,0x9a = csinc x19, x23, x29, lt 513 0x7f,0xa4,0x84,0x9a = csinc xzr, x3, x4, ge 514 0xe5,0x27,0x86,0x9a = csinc x5, xzr, x6, hs 515 0x07,0x35,0x9f,0x9a = csinc x7, x8, xzr, lo`

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