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/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc11712 ZRegister dm_result = z4.WithLaneSize(lane_size_in_bits); in SdotUdotHelper() local
11726 __ Mov(dm_result, zm.WithSameLaneSizeAs(dm_result)); in SdotUdotHelper()
11728 dot_fn(dm_result, za, zn, dm_result.WithSameLaneSizeAs(zm), is_signed, index); in SdotUdotHelper()
11754 ASSERT_EQUAL_SVE(zd_expected, dm_result); in SdotUdotHelper()
12384 ZRegister dm_result = z1.WithLaneSize(lane_size_in_bits); in FPBinArithHelper() local
12385 __ Mov(dm_result, zm); in FPBinArithHelper()
12387 (masm.*macro)(dm_result, pg.Merging(), zn, dm_result, nan_option); in FPBinArithHelper()
12389 (masm.*macro_nonan)(dm_result, pg.Merging(), zn, dm_result); in FPBinArithHelper()
12423 if (!core.HasSVELane(dm_result, lane)) break; in FPBinArithHelper()
12425 ASSERT_EQUAL_SVE_LANE(zd_expected[i], dm_result, lane); in FPBinArithHelper()
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