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/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc11715 ZRegister dn_result = z7.WithLaneSize(lane_size_in_bits); in SdotUdotHelper() local
11722 __ Mov(dn_result, zn.WithSameLaneSizeAs(dn_result)); in SdotUdotHelper()
11724 dot_fn(dn_result, za, dn_result.WithSameLaneSizeAs(zn), zm, is_signed, index); in SdotUdotHelper()
11753 ASSERT_EQUAL_SVE(zd_expected, dn_result); in SdotUdotHelper()
12372 ZRegister dn_result = z0.WithLaneSize(lane_size_in_bits); in FPBinArithHelper() local
12373 __ Mov(dn_result, zn); in FPBinArithHelper()
12375 (masm.*macro)(dn_result, pg.Merging(), dn_result, zm, nan_option); in FPBinArithHelper()
12377 (masm.*macro_nonan)(dn_result, pg.Merging(), dn_result, zm); in FPBinArithHelper()
12413 if (!core.HasSVELane(dn_result, lane)) break; in FPBinArithHelper()
12415 ASSERT_EQUAL_SVE_LANE(zd_expected[i], dn_result, lane); in FPBinArithHelper()
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