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/external/virglrenderer/src/gallium/auxiliary/util/
Du_format.c278 const struct util_format_description *dst_desc) in util_is_format_compatible() argument
282 if (src_desc->format == dst_desc->format) { in util_is_format_compatible()
287 dst_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) { in util_is_format_compatible()
291 if (src_desc->block.bits != dst_desc->block.bits || in util_is_format_compatible()
292 src_desc->nr_channels != dst_desc->nr_channels || in util_is_format_compatible()
293 src_desc->colorspace != dst_desc->colorspace) { in util_is_format_compatible()
299 dst_desc->channel[chan].size) { in util_is_format_compatible()
305 enum util_format_swizzle swizzle = dst_desc->swizzle[chan]; in util_is_format_compatible()
312 dst_desc->channel[swizzle].type) || in util_is_format_compatible()
314 dst_desc->channel[swizzle].normalized)) { in util_is_format_compatible()
/external/tensorflow/tensorflow/lite/delegates/gpu/common/tasks/
Dsoftmax.cc73 auto dst_desc = definition.dst_tensors[0]; in CreateSoftmax() local
75 dst_desc.SetStateVar("BatchedWidth", "true"); in CreateSoftmax()
77 op.AddDstTensor("dst_tensor", dst_desc); in CreateSoftmax()
Dresize.cc47 auto dst_desc = op_def.dst_tensors[0]; in GetResizeCode() local
49 dst_desc.SetStateVar("BatchedWidth", "true"); in GetResizeCode()
51 AddDstTensor("dst_tensor", dst_desc); in GetResizeCode()
182 auto dst_desc = op_def.dst_tensors[0]; in GetResize3DCode() local
184 dst_desc.SetStateVar("BatchedWidth", "true"); in GetResize3DCode()
186 AddDstTensor("dst_tensor", dst_desc); in GetResize3DCode()
Dpooling.cc36 auto dst_desc = op_def.dst_tensors[0]; in GetAveragePoolingKernelCode() local
38 dst_desc.SetStateVar("BatchedWidth", "true"); in GetAveragePoolingKernelCode()
40 op->AddDstTensor("dst_tensor", dst_desc); in GetAveragePoolingKernelCode()
153 auto dst_desc = op_def.dst_tensors[0]; in GetMaxPoolingKernelCode() local
155 dst_desc.SetStateVar("BatchedWidth", "true"); in GetMaxPoolingKernelCode()
157 op->AddDstTensor("dst_tensor", dst_desc); in GetMaxPoolingKernelCode()
Dconcat_z.cc134 auto dst_desc = definition.dst_tensors[0]; in CreateConcatZ() local
136 dst_desc.SetStateVar("BatchedWidth", "true"); in CreateConcatZ()
138 op.AddDstTensor("dst_tensor", dst_desc); in CreateConcatZ()
Dmax_unpooling.cc40 auto dst_desc = op_def.dst_tensors[0]; in GetMaxUnpoolingKernelCode() local
42 dst_desc.SetStateVar("BatchedWidth", "true"); in GetMaxUnpoolingKernelCode()
44 op->AddDstTensor("dst_tensor", dst_desc); in GetMaxUnpoolingKernelCode()
Dconv_constants.cc109 auto dst_desc = op_def.dst_tensors[0]; in GenerateConvolutionConstantCode() local
111 dst_desc.SetStateVar("BatchedWidth", "true"); in GenerateConvolutionConstantCode()
113 op->AddDstTensor("dst_tensor", dst_desc); in GenerateConvolutionConstantCode()
Dconvolution_transposed_4x4.cc81 auto dst_desc = op_def.dst_tensors[0]; in GenerateConvolutionTransposedCode() local
83 dst_desc.SetStateVar("BatchedWidth", "true"); in GenerateConvolutionTransposedCode()
85 AddDstTensor("dst_tensor", dst_desc); in GenerateConvolutionTransposedCode()
Ddepthwise_conv.cc82 auto dst_desc = op_def.dst_tensors[0]; in GenerateDepthwiseConvolutionCode() local
84 dst_desc.SetStateVar("BatchedWidth", "true"); in GenerateDepthwiseConvolutionCode()
86 op->AddDstTensor("dst_tensor", dst_desc); in GenerateDepthwiseConvolutionCode()
Dconvolution_transposed_3x3.cc66 auto dst_desc = op_def.dst_tensors[0]; in GenerateConvolutionTransposedCode() local
68 dst_desc.SetStateVar("BatchedWidth", "true"); in GenerateConvolutionTransposedCode()
70 AddDstTensor("dst_tensor", dst_desc); in GenerateConvolutionTransposedCode()
Dconv_buffer_1x1.cc189 auto dst_desc = op_def.dst_tensors[0]; in GenerateConvBuffer1x1() local
191 dst_desc.SetStateVar("BatchedWidth", "true"); in GenerateConvBuffer1x1()
193 AddDstTensor("dst_tensor", dst_desc); in GenerateConvBuffer1x1()
Dconv_metal.cc1005 auto dst_desc = definition.dst_tensors[0]; in CreateConvolutionMetal() local
1007 dst_desc.SetStateVar("BatchedWidth", "true"); in CreateConvolutionMetal()
1009 desc.AddDstTensor("dst_tensor", dst_desc); in CreateConvolutionMetal()
1130 auto dst_desc = definition.dst_tensors[0]; in CreateConvolutionMetalWino4x4To6x6() local
1132 dst_desc.SetStateVar("BatchedWidth", "true"); in CreateConvolutionMetalWino4x4To6x6()
1134 desc.AddDstTensor("dst_tensor", dst_desc); in CreateConvolutionMetalWino4x4To6x6()
/external/mesa3d/src/mesa/state_tracker/
Dst_cb_copyimage.c289 const struct util_format_description *src_desc, *dst_desc; in swizzled_copy() local
306 dst_desc = util_format_description(blit_dst_format); in swizzled_copy()
308 assert(src_desc->block.bits == dst_desc->block.bits); in swizzled_copy()
311 if (dst_desc->channel[0].size == src_desc->channel[0].size) { in swizzled_copy()
321 canonical_format_from_bits(bits, dst_desc->channel[0].size); in swizzled_copy()
322 } else if (has_identity_swizzle(dst_desc)) { in swizzled_copy()
412 const struct util_format_description *src_desc, *dst_desc; in handle_complex_copy() local
420 dst_desc = util_format_description(dst->format); in handle_complex_copy()
425 dst_is_canon = same_size_and_swizzle(dst_desc, canon_desc); in handle_complex_copy()
427 dst_is_noncanon = same_size_and_swizzle(dst_desc, noncanon_desc); in handle_complex_copy()
/external/mesa3d/src/util/format/
Du_format.c444 const struct util_format_description *dst_desc) in util_is_format_compatible() argument
448 if (src_desc->format == dst_desc->format) { in util_is_format_compatible()
453 dst_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) { in util_is_format_compatible()
457 if (src_desc->block.bits != dst_desc->block.bits || in util_is_format_compatible()
458 src_desc->nr_channels != dst_desc->nr_channels || in util_is_format_compatible()
459 src_desc->colorspace != dst_desc->colorspace) { in util_is_format_compatible()
465 dst_desc->channel[chan].size) { in util_is_format_compatible()
471 enum pipe_swizzle swizzle = dst_desc->swizzle[chan]; in util_is_format_compatible()
478 dst_desc->channel[swizzle].type) || in util_is_format_compatible()
480 dst_desc->channel[swizzle].normalized)) { in util_is_format_compatible()
/external/tensorflow/tensorflow/lite/delegates/gpu/common/task/
Dgpu_operation.cc196 auto dst_desc = in AssembleCode() local
199 dst_desc->SetStateVar("BatchedWidth", "true"); in AssembleCode()
202 args_.AddObjectRef("dst_tensor", AccessType::WRITE, std::move(dst_desc)); in AssembleCode()
/external/tensorflow/tensorflow/core/util/
Dmkl_types.h48 #define GET_DST_DESC_FROM_OP_PD(op_pd) op_pd->dst_desc()
107 #define PRIMITIVE_DESC_DST dst_desc()
/external/tensorflow/tensorflow/core/kernels/mkl/
Dmkl_softmax_op.cc130 new memory(context_.fwd_pd.get()->dst_desc(), cpu_engine_, DummyData)); in Setup()
280 auto dst_pd = softmax_fwd->GetSoftmaxFwdPd()->dst_desc(); in Compute()
Dmkl_aggregate_ops.cc219 auto output_pd = sum_pd.dst_desc(); in Compute()
Dmkl_matmul_ops_common.h270 new memory(context_.fwd_pd.get()->dst_desc(), cpu_engine_, DummyData)); in Setup()
395 auto dst_pd = mkldnn_matmul_prim_desc.dst_desc(); in AllocateOutputTensor()
/external/mesa3d/src/gallium/frontends/lavapipe/
Dlvp_descriptor_set.c427 struct lvp_descriptor *dst_desc = in lvp_UpdateDescriptorSets() local
429 dst_desc += copy->dstArrayElement; in lvp_UpdateDescriptorSets()
432 dst_desc[j] = src_desc[j]; in lvp_UpdateDescriptorSets()
/external/mesa3d/src/gallium/auxiliary/util/
Du_surface.c741 const struct util_format_description *src_desc, *dst_desc; in util_can_blit_via_copy_region() local
744 dst_desc = util_format_description(blit->dst.resource->format); in util_can_blit_via_copy_region()
756 !util_is_format_compatible(src_desc, dst_desc)) { in util_can_blit_via_copy_region()
/external/mesa3d/src/gallium/drivers/svga/
Dsvga_pipe_blit.c421 const struct util_format_description *src_desc, *dst_desc; in can_blit_via_surface_copy() local
424 dst_desc = util_format_description(blit_info->dst.resource->format); in can_blit_via_surface_copy()
428 !util_is_format_compatible(src_desc, dst_desc)) in can_blit_via_surface_copy()
/external/virglrenderer/src/
Dvrend_blitter.c714 const struct util_format_description *dst_desc = in vrend_renderer_blit_gl() local
721 util_format_has_depth(dst_desc); in vrend_renderer_blit_gl()
723 util_format_has_stencil(dst_desc); in vrend_renderer_blit_gl()
Dvrend_formats.c881 const struct util_format_description *dst_desc = util_format_description(dst); in format_is_copy_compatible() local
882 return util_is_format_compatible(src_desc, dst_desc); in format_is_copy_compatible()
/external/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_blitter.c217 const struct util_format_description *dst_desc = in can_do_blit() local
219 const int common_channels = MIN2(src_desc->nr_channels, dst_desc->nr_channels); in can_do_blit()
224 &dst_desc->channel[i], in can_do_blit()

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