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/external/capstone/suite/MC/SystemZ/
Dinsn-good.s.cs15 0xed,0xf0,0x00,0x00,0x00,0x1a = adb %f15, 0
17 0xb3,0x1a,0x00,0x0f = adbr %f0, %f15
19 0xb3,0x1a,0x00,0xf0 = adbr %f15, %f0
26 0xed,0xf0,0x00,0x00,0x00,0x0a = aeb %f15, 0
28 0xb3,0x0a,0x00,0x0f = aebr %f0, %f15
30 0xb3,0x0a,0x00,0xf0 = aebr %f15, %f0
278 0xed,0xf0,0x00,0x00,0x00,0x19 = cdb %f15, 0
280 0xb3,0x19,0x00,0x0f = cdbr %f0, %f15
282 0xb3,0x19,0x00,0xf0 = cdbr %f15, %f0
285 0xb3,0x95,0x00,0xf0 = cdfbr %f15, %r0
[all …]
Dregs-good.s.cs33 0x38,0xef = ler %f14, %f15
41 0x28,0xef = ldr %f14, %f15
/external/mesa3d/src/mesa/sparc/
Dnorm.S29 ld [%sp + STACK_VAR_OFF+0x4], %f15 ! f15 = scale
104 fmuls M0, %f15, M0
105 fmuls M1, %f15, M1
106 fmuls M2, %f15, M2
107 fmuls M4, %f15, M4
108 fmuls M5, %f15, M5
109 fmuls M6, %f15, M6
110 fmuls M8, %f15, M8
111 fmuls M9, %f15, M9
112 fmuls M10, %f15, M10
[all …]
/external/llvm-project/llvm/test/MC/SystemZ/
Dinsn-good.s41 #CHECK: ad %f15, 0 # encoding: [0x6a,0xf0,0x00,0x00]
49 ad %f15, 0
57 #CHECK: adb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x1a]
65 adb %f15, 0
68 #CHECK: adbr %f0, %f15 # encoding: [0xb3,0x1a,0x00,0x0f]
70 #CHECK: adbr %f15, %f0 # encoding: [0xb3,0x1a,0x00,0xf0]
73 adbr %f0, %f15
75 adbr %f15, %f0
78 #CHECK: adr %f0, %f15 # encoding: [0x2a,0x0f]
80 #CHECK: adr %f15, %f0 # encoding: [0x2a,0xf0]
[all …]
Dinsn-good-z196.s7 #CHECK: adtra %f0, %f0, %f15, 0 # encoding: [0xb3,0xd2,0xf0,0x00]
8 #CHECK: adtra %f0, %f15, %f0, 0 # encoding: [0xb3,0xd2,0x00,0x0f]
9 #CHECK: adtra %f15, %f0, %f0, 0 # encoding: [0xb3,0xd2,0x00,0xf0]
14 adtra %f0, %f0, %f15, 0
15 adtra %f0, %f15, %f0, 0
16 adtra %f15, %f0, %f0, 0
285 #CHECK: cdfbra %f15, 0, %r0, 0 # encoding: [0xb3,0x95,0x00,0xf0]
292 cdfbra %f15, 0, %r0, 0
299 #CHECK: cdftr %f15, 0, %r0, 0 # encoding: [0xb9,0x51,0x00,0xf0]
306 cdftr %f15, 0, %r0, 0
[all …]
Dregs-good.s70 #CHECK: ler %f14, %f15 # encoding: [0x38,0xef]
71 #CHECK: ler %f0, %f15 # encoding: [0x38,0x0f]
80 ler %f14,%f15
90 #CHECK: ldr %f14, %f15 # encoding: [0x28,0xef]
91 #CHECK: ldr %f0, %f15 # encoding: [0x28,0x0f]
100 ldr %f14,%f15
210 #CHECK: .cfi_offset %f15, 248
276 .cfi_offset %f15,248
/external/llvm-project/llvm/test/MC/Disassembler/SystemZ/
Dinsns.txt43 # CHECK: ad %f15, 0
64 # CHECK: adb %f15, 0
70 # CHECK: adbr %f0, %f15
76 # CHECK: adbr %f15, %f0
82 # CHECK: adr %f0, %f15
88 # CHECK: adr %f15, %f0
94 # CHECK: adtr %f0, %f0, %f15
97 # CHECK: adtr %f0, %f15, %f0
100 # CHECK: adtr %f15, %f0, %f0
112 # CHECK: adtra %f0, %f0, %f15, 1
[all …]
/external/llvm/test/CodeGen/Mips/
Dselect.ll221 ; 64: c.eq.s $f14, $f15
225 ; 64R2: c.eq.s $f14, $f15
229 ; 64R6: cmp.eq.s $[[CC:f0]], $f14, $f15
258 ; 64: c.olt.s $f14, $f15
262 ; 64R2: c.olt.s $f14, $f15
266 ; 64R6: cmp.lt.s $[[CC:f0]], $f14, $f15
295 ; 64: c.ule.s $f14, $f15
299 ; 64R2: c.ule.s $f14, $f15
303 ; 64R6: cmp.lt.s $[[CC:f0]], $f15, $f14
332 ; 64: c.ule.s $f14, $f15
[all …]
/external/llvm/test/MC/SystemZ/
Dinsn-good.s26 #CHECK: adb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x1a]
34 adb %f15, 0
37 #CHECK: adbr %f0, %f15 # encoding: [0xb3,0x1a,0x00,0x0f]
39 #CHECK: adbr %f15, %f0 # encoding: [0xb3,0x1a,0x00,0xf0]
42 adbr %f0, %f15
44 adbr %f15, %f0
52 #CHECK: aeb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x0a]
60 aeb %f15, 0
63 #CHECK: aebr %f0, %f15 # encoding: [0xb3,0x0a,0x00,0x0f]
65 #CHECK: aebr %f15, %f0 # encoding: [0xb3,0x0a,0x00,0xf0]
[all …]
Dregs-good.s64 #CHECK: ler %f14, %f15 # encoding: [0x38,0xef]
73 ler %f14,%f15
82 #CHECK: ldr %f14, %f15 # encoding: [0x28,0xef]
91 ldr %f14,%f15
134 #CHECK: .cfi_offset %f15, 248
168 .cfi_offset %f15,248
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Danyregcc-novec.ll24 ;CHECK: std %f15,
33 …f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15}"() nounwind
50 ;CHECK-NEXT: std %f15,
67 %a15 = call double asm sideeffect "", "={f15}"() nounwind
69 …f1},{f2},{f3},{f4},{f5},{f6},{f7},{f8},{f9},{f10},{f11},{f12},{f13},{f14},{f15}"(double %a0, doubl…
Dframe-07.ll22 ; CHECK-NOFP: std %f15, 4064(%r15)
30 ; CHECK-NOFP: .cfi_offset %f15, -224
39 ; CHECK-NOFP: ld %f15, 4064(%r15)
56 ; CHECK-FP: std %f15, 4064(%r11)
65 ; CHECK-FP: ld %f15, 4064(%r11)
143 ; CHECK-NOFP: stdy %f15, 524256(%r15)
151 ; CHECK-NOFP: .cfi_offset %f15, -224
160 ; CHECK-NOFP: ldy %f15, 524256(%r15)
176 ; CHECK-FP: stdy %f15, 524256(%r11)
184 ; CHECK-FP: .cfi_offset %f15, -224
[all …]
Dframe-04.ll21 ; CHECK: std %f15, 0(%r15)
29 ; CHECK: .cfi_offset %f15, -224
38 ; CHECK: ld %f15, 0(%r15)
69 ; so %f13+%f15 is the pair that gets dropped.
87 ; CHECK-NOT: %f15
136 ; CHECK-NOT: %f15
172 ; CHECK-NOT: %f15
Dframe-17.ll18 ; CHECK: std %f15, 168(%r15)
31 ; CHECK: ld %f15, 168(%r15)
82 ; CHECK: std %f15, 168(%r15)
92 ; CHECK: ld %f15, 168(%r15)
143 ; CHECK: std %f15, 176(%r15)
155 ; CHECK: ld %f15, 176(%r15)
/external/llvm-project/llvm/test/CodeGen/Mips/
Dselect.ll311 ; 64-NEXT: c.eq.s $f14, $f15
318 ; 64R2-NEXT: c.eq.s $f14, $f15
324 ; 64R6-NEXT: cmp.eq.s $f0, $f14, $f15
363 ; 64-NEXT: c.olt.s $f14, $f15
370 ; 64R2-NEXT: c.olt.s $f14, $f15
376 ; 64R6-NEXT: cmp.lt.s $f0, $f14, $f15
415 ; 64-NEXT: c.ule.s $f14, $f15
422 ; 64R2-NEXT: c.ule.s $f14, $f15
428 ; 64R6-NEXT: cmp.lt.s $f0, $f15, $f14
469 ; 64-NEXT: c.ule.s $f14, $f15
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dframe-07.ll22 ; CHECK-NOFP: std %f15, 4064(%r15)
30 ; CHECK-NOFP: .cfi_offset %f15, -224
39 ; CHECK-NOFP: ld %f15, 4064(%r15)
56 ; CHECK-FP: std %f15, 4064(%r11)
65 ; CHECK-FP: ld %f15, 4064(%r11)
143 ; CHECK-NOFP: stdy %f15, 524256(%r15)
151 ; CHECK-NOFP: .cfi_offset %f15, -224
160 ; CHECK-NOFP: ldy %f15, 524256(%r15)
176 ; CHECK-FP: stdy %f15, 524256(%r11)
184 ; CHECK-FP: .cfi_offset %f15, -224
[all …]
Dframe-04.ll21 ; CHECK: std %f15, 160(%r15)
29 ; CHECK: .cfi_offset %f15, -224
38 ; CHECK: ld %f15, 160(%r15)
69 ; so %f13+%f15 is the pair that gets dropped.
87 ; CHECK-NOT: %f15
136 ; CHECK-NOT: %f15
172 ; CHECK-NOT: %f15
Dframe-17.ll18 ; CHECK: std %f15, 168(%r15)
31 ; CHECK: ld %f15, 168(%r15)
82 ; CHECK: std %f15, 168(%r15)
92 ; CHECK: ld %f15, 168(%r15)
143 ; CHECK: std %f15, 176(%r15)
155 ; CHECK: ld %f15, 176(%r15)
/external/linux-kselftest/tools/testing/selftests/powerpc/include/
Dfpu_asm.h27 stfd f15,(stack_size + STACK_FRAME_MIN_SIZE - 128)(%r1); \
47 lfd f15,(stack_size + STACK_FRAME_MIN_SIZE - 128)(%r1); \
56 lfd f15,8(r3)
/external/llvm/test/MC/Disassembler/SystemZ/
Dinsns.txt7 # CHECK: adbr %f0, %f15
13 # CHECK: adbr %f15, %f0
34 # CHECK: adb %f15, 0
40 # CHECK: aebr %f0, %f15
46 # CHECK: aebr %f15, %f0
67 # CHECK: aeb %f15, 0
850 # CHECK: cdbr %f0, %f15
856 # CHECK: cdbr %f15, %f0
877 # CHECK: cdb %f15, 0
886 # CHECK: cdfbr %f15, %r0
[all …]
/external/clang/test/CXX/except/except.spec/
Dp5-virtual.cpp45 virtual void f15();
81 virtual void f15() noexcept;
/external/llvm-project/clang/test/CXX/except/except.spec/
Dp5-virtual.cpp45 virtual void f15();
81 virtual void f15() noexcept;
/external/libffi/src/ia64/
Dunix.S74 ldf.fill f15 = [r16], 24
226 (p7) stfs [r16] = f15
250 (p7) stfd [r16] = f15
274 (p7) stfe [r16] = f15
324 stf.spill [r17] = f15, 24
455 (p7) ldfs f15 = [r17]
483 (p7) ldfd f15 = [r17]
511 (p7) ldfe f15 = [r17]
/external/python/cpython2/Modules/_ctypes/libffi/src/ia64/
Dunix.S74 ldf.fill f15 = [r16], 24
221 (p7) stfs [r16] = f15
245 (p7) stfd [r16] = f15
269 (p7) stfe [r16] = f15
319 stf.spill [r17] = f15, 24
450 (p7) ldfs f15 = [r17]
478 (p7) ldfd f15 = [r17]
506 (p7) ldfe f15 = [r17]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dppc64-fastcc.ll7 …, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i6…
15 …, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i6…
23 …, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i6…
31 …, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i6…
39 …, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i6…
47 …, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i6…
55 …, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i6…
63 …, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i6…
71 …, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i6…
79 …, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i6…
[all …]

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