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Searched refs:fcvtzs (Results 1 – 25 of 111) sorted by relevance

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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dfcvtzs.s10 fcvtzs z0.h, p0/m, z0.h label
16 fcvtzs z0.s, p0/m, z0.h label
22 fcvtzs z0.s, p0/m, z0.s label
28 fcvtzs z0.s, p0/m, z0.d label
34 fcvtzs z0.d, p0/m, z0.h label
40 fcvtzs z0.d, p0/m, z0.s label
46 fcvtzs z0.d, p0/m, z0.d label
62 fcvtzs z5.d, p0/m, z0.d label
74 fcvtzs z5.d, p0/m, z0.d label
Dfcvtzs-diagnostics.s3 fcvtzs z0.h, p0/m, z0.s label
8 fcvtzs z0.h, p0/m, z0.d label
17 fcvtzs z0.h, p8/m, z0.h label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dcomplex-fp-to-int.ll6 ; CHECK: fcvtzs.2d v0, [[VAL64]]
23 ; CHECK: fcvtzs.2s v0, v0
31 ; CHECK: fcvtzs.2s v0, v0
39 ; CHECK: fcvtzs.2s v0, v0
47 ; CHECK: fcvtzs.2s v0, v0
55 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
73 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
82 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
91 ; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
109 ; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
[all …]
Darm64-convert-v4f64.ll6 ; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d
7 ; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d
18 ; CHECK-DAG: fcvtzs v[[CONV0:[0-9]+]].2d, v0.2d
19 ; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d
20 ; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d
21 ; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d
58 ; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d
59 ; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d
Dfcvt_combine.ll5 ; CHECK: fcvtzs.2s v0, v0, #4
15 ; CHECK: fcvtzs.4s v0, v0, #3
25 ; CHECK: fcvtzs.2d v0, v0, #5
36 ; CHECK: fcvtzs.2d v0, v0
48 ; CHECK: fcvtzs.2s v0, v0, #4
61 ; CHECK: fcvtzs.2d v0, v0
126 ; CHECK: fcvtzs.2s v0, v0
137 ; CHECK: fcvtzs.2s v0, v0
147 ; CHECK: fcvtzs.2s v0, v0, #32
156 ; CHECK: fcvtzs.4s v0, v0, #2
Dlrint-conv-win.ll5 ; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]]
17 ; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]]
27 ; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]]
39 ; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]]
Dllrint-conv.ll5 ; CHECK-NEXT: fcvtzs x0, [[REG]]
16 ; CHECK-NEXT: fcvtzs x0, [[REG]]
26 ; CHECK-NEXT: fcvtzs x0, [[REG]]
37 ; CHECK-NEXT: fcvtzs x0, [[REG]]
Dfcvt-fixed.ll15 ; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #7
20 ; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #32
25 ; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #7
30 ; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #64
35 ; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #7
40 ; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #32
45 ; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #7
50 ; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #64
Dlrint-conv-fp16.ll5 ; CHECK-NEXT: fcvtzs x0, h0
16 ; CHECK-NEXT: fcvtzs x0, h0
27 ; CHECK-NEXT: fcvtzs x0, h0
Dllrint-conv-fp16.ll5 ; CHECK-NEXT: fcvtzs x0, h0
16 ; CHECK-NEXT: fcvtzs x0, h0
27 ; CHECK-NEXT: fcvtzs x0, h0
Dlrint-conv-fp16-win.ll5 ; CHECK-NEXT: fcvtzs w0, h0
16 ; CHECK-NEXT: fcvtzs w0, h0
26 ; CHECK-NEXT: fcvtzs w8, h0
Dlrint-conv.ll6 ; CHECK-NEXT: fcvtzs x0, [[REG]]
18 ; CHECK-NEXT: fcvtzs x0, [[REG]]
29 ; CHECK-NEXT: fcvtzs x0, [[REG]]
41 ; CHECK-NEXT: fcvtzs x0, [[REG]]
Dfp16_intrinsic_scalar_1op.ll19 declare i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half)
20 declare i32 @llvm.aarch64.neon.fcvtzs.i32.f16(half)
111 ; CHECK: fcvtzs w0, h0
120 ; CHECK: fcvtzs x0, h0
129 ; CHECK: fcvtzs w0, h0
156 ; CHECK: fcvtzs x0, h0
159 %fcvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half %a)
165 ; CHECK: fcvtzs w0, h0
168 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f16(half %a)
174 ; CHECK: fcvtzs x0, h0
[all …]
Dsve-intrinsics-fp-converts.ll77 ; CHECK: fcvtzs z0.h, p0/m, z1.h
79 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> %a,
87 ; CHECK: fcvtzs z0.s, p0/m, z1.s
89 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.nxv4i32.nxv4f32(<vscale x 4 x i32> %a,
97 ; CHECK: fcvtzs z0.d, p0/m, z1.d
99 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.nxv2i64.nxv2f64(<vscale x 2 x i64> %a,
107 ; CHECK: fcvtzs z0.s, p0/m, z1.h
109 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> %a,
117 ; CHECK: fcvtzs z0.s, p0/m, z1.d
119 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> %a,
[all …]
/external/llvm/test/CodeGen/AArch64/
Dcomplex-fp-to-int.ll6 ; CHECK: fcvtzs.2d v0, [[VAL64]]
23 ; CHECK: fcvtzs.2s v0, v0
31 ; CHECK: fcvtzs.2s v0, v0
39 ; CHECK: fcvtzs.2s v0, v0
47 ; CHECK: fcvtzs.2s v0, v0
55 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
73 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
82 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
91 ; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
109 ; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
[all …]
Darm64-convert-v4f64.ll6 ; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d
7 ; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d
18 ; CHECK-DAG: fcvtzs v[[CONV0:[0-9]+]].2d, v0.2d
19 ; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d
20 ; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d
21 ; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d
Dfcvt_combine.ll5 ; CHECK: fcvtzs.2s v0, v0, #4
15 ; CHECK: fcvtzs.4s v0, v0, #3
25 ; CHECK: fcvtzs.2d v0, v0, #5
36 ; CHECK: fcvtzs.2d v0, v0
48 ; CHECK: fcvtzs.2s v0, v0, #4
61 ; CHECK: fcvtzs.2d v0, v0
127 ; CHECK: fcvtzs.2s v0, v0
138 ; CHECK: fcvtzs.2s v0, v0
148 ; CHECK: fcvtzs.2s v0, v0, #32
157 ; CHECK: fcvtzs.4s v0, v0, #2
Dfcvt-fixed.ll15 ; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #7
20 ; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #32
25 ; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #7
30 ; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #64
35 ; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #7
40 ; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #32
45 ; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #7
50 ; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #64
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Exynos/
Dfloat-integer.s10 fcvtzs w3, h3 label
11 fcvtzs w4, s4 label
12 fcvtzs x5, d5 label
67 # EM3-NEXT: 1 3 1.00 fcvtzs w4, s4
68 # EM3-NEXT: 1 3 1.00 fcvtzs x5, d5
82 # EM4-NEXT: 1 4 1.00 fcvtzs w3, h3
83 # EM4-NEXT: 1 4 1.00 fcvtzs w4, s4
84 # EM4-NEXT: 1 4 1.00 fcvtzs x5, d5
101 # EM5-NEXT: 1 4 1.00 fcvtzs w3, h3
102 # EM5-NEXT: 1 4 1.00 fcvtzs w4, s4
[all …]
/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s57 fcvtzs h21, h12, #1
58 fcvtzs s21, s12, #1
59 fcvtzs d21, d12, #1
194 fcvtzs h12, h13
195 fcvtzs s12, s13
196 fcvtzs d21, d14
Darm64-fp-encoding.s398 fcvtzs w1, h2
399 fcvtzs w1, h2, #1
400 fcvtzs w1, s2
401 fcvtzs w1, s2, #1
402 fcvtzs w1, d2
403 fcvtzs w1, d2, #1
404 fcvtzs x1, h2
405 fcvtzs x1, h2, #1
406 fcvtzs x1, s2
407 fcvtzs x1, s2, #1
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s57 fcvtzs h21, h12, #1
58 fcvtzs s21, s12, #1
59 fcvtzs d21, d12, #1
194 fcvtzs h12, h13
195 fcvtzs s12, s13
196 fcvtzs d21, d14
Darm64-fp-encoding.s398 fcvtzs w1, h2
399 fcvtzs w1, h2, #1
400 fcvtzs w1, s2
401 fcvtzs w1, s2, #1
402 fcvtzs w1, d2
403 fcvtzs w1, d2, #1
404 fcvtzs x1, h2
405 fcvtzs x1, h2, #1
406 fcvtzs x1, s2
407 fcvtzs x1, s2, #1
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-scalar-cvt.s.cs10 0x95,0xfd,0x3f,0x5f = fcvtzs s21, s12, #1
11 0x95,0xfd,0x7f,0x5f = fcvtzs d21, d12, #1
31 0xac,0xb9,0xa1,0x5e = fcvtzs s12, s13
32 0xd5,0xb9,0xe1,0x5e = fcvtzs d21, d14
/external/vixl/test/aarch64/
Dtest-disasm-fp-aarch64.cc290 COMPARE(fcvtzs(x20, d21), "fcvtzs x20, d21"); in TEST()
291 COMPARE(fcvtzs(w22, d23), "fcvtzs w22, d23"); in TEST()
294 COMPARE(fcvtzs(x20, s21), "fcvtzs x20, s21"); in TEST()
295 COMPARE(fcvtzs(w22, s23), "fcvtzs w22, s23"); in TEST()
296 COMPARE(fcvtzs(w2, d1, 1), "fcvtzs w2, d1, #1"); in TEST()
297 COMPARE(fcvtzs(w2, s1, 1), "fcvtzs w2, s1, #1"); in TEST()
298 COMPARE(fcvtzs(x4, d3, 15), "fcvtzs x4, d3, #15"); in TEST()
299 COMPARE(fcvtzs(x4, s3, 15), "fcvtzs x4, s3, #15"); in TEST()
300 COMPARE(fcvtzs(w6, d5, 32), "fcvtzs w6, d5, #32"); in TEST()
301 COMPARE(fcvtzs(w6, s5, 32), "fcvtzs w6, s5, #32"); in TEST()
[all …]

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