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Searched refs:fmask_size (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_surface.c406 surf_ws->fmask_size = fmask.surf_size; in radeon_winsys_surface_init()
421 (tex->nr_samples <= 1 || surf_ws->fmask_size)) { in radeon_winsys_surface_init()
446 if (surf_ws->fmask_size) { in radeon_winsys_surface_init()
449 surf_ws->total_size = surf_ws->fmask_offset + surf_ws->fmask_size; in radeon_winsys_surface_init()
/external/mesa3d/src/amd/common/
Dac_surface.h232 uint64_t fmask_size; member
Dac_surface.c779 (config->info.samples >= 2 && !surf->fmask_size)) in ac_compute_cmask()
1139 surf->fmask_size = fout.fmaskBytes; in gfx6_compute_surface()
1705 surf->fmask_size = fout.fmaskBytes; in gfx9_compute_miptree()
1739 (surf->fmask_size && in->numSamples >= 2))) { in gfx9_compute_miptree()
1942 surf->fmask_size = 0; in gfx9_compute_surface()
2121 if (surf->fmask_size) { in ac_compute_surface()
2124 surf->total_size = surf->fmask_offset + surf->fmask_size; in ac_compute_surface()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_blit.c444 } else if (tex->surface.fmask_size) { in si_blit_decompress_color()
508 if (!tex->cmask_buffer && !tex->surface.fmask_size && in si_decompress_color_texture()
798 } else if (stex->surface.fmask_size || stex->cmask_buffer || in si_decompress_subresource()
Dsi_texture.c543 assert(!tex->surface.fmask_size); in si_reallocate_texture_inplace()
561 assert(tex->surface.fmask_size == 0); in si_set_tex_bo_metadata()
854 tex->surface.fmask_offset, tex->surface.fmask_size, in si_print_texture_info()
903 tex->surface.fmask_offset, tex->surface.fmask_size, tex->surface.fmask_alignment, in si_print_texture_info()
Dsi_clear.c570 if (tex->surface.fmask_size == 0) in si_clear()
Dsi_descriptors.c474 if (!is_buffer && tex->surface.fmask_size) { in si_set_sampler_view_desc()
487 return tex->surface.fmask_size || in color_needs_decompression()
958 if (tex && tex->surface.fmask_size) in si_bind_sampler_states()
Dsi_compute_blit.c755 si_clear_buffer(sctx, tex, stex->surface.fmask_offset, stex->surface.fmask_size, in si_compute_expand_fmask()
Dsi_state.c2348 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) { in si_initialize_color_surface()
/external/mesa3d/src/amd/vulkan/
Dradv_meta_clear.c1507 size = image->planes[0].surface.fmask_size; in radv_clear_fmask()