| /external/llvm-project/llvm/test/CodeGen/RISCV/ |
| D | callee-saved-fpr32s.ll | 60 ; ILP32-NEXT: fsw fs8, 124(a1)
61 ; ILP32-NEXT: fsw fs9, 120(a1)
62 ; ILP32-NEXT: fsw fs10, 116(a1)
63 ; ILP32-NEXT: fsw fs11, 112(a1)
64 ; ILP32-NEXT: fsw fs7, 108(a1)
65 ; ILP32-NEXT: fsw fs6, 104(a1)
66 ; ILP32-NEXT: fsw fs5, 100(a1)
67 ; ILP32-NEXT: fsw fs4, 96(a1)
68 ; ILP32-NEXT: fsw fs3, 92(a1)
69 ; ILP32-NEXT: fsw fs2, 88(a1)
[all …]
|
| D | fastcc-float.ll | 53 ; CHECK-NEXT: fsw fs11, 44(sp)
54 ; CHECK-NEXT: fsw fs10, 40(sp)
55 ; CHECK-NEXT: fsw fs9, 36(sp)
56 ; CHECK-NEXT: fsw fs8, 32(sp)
57 ; CHECK-NEXT: fsw fs7, 28(sp)
58 ; CHECK-NEXT: fsw fs6, 24(sp)
59 ; CHECK-NEXT: fsw fs5, 20(sp)
60 ; CHECK-NEXT: fsw fs4, 16(sp)
61 ; CHECK-NEXT: fsw fs3, 12(sp)
62 ; CHECK-NEXT: fsw fs2, 8(sp)
[all …]
|
| D | interrupt-attr.ll | 112 ; CHECK-RV32-F-NEXT: fsw ft0, 124(sp)
113 ; CHECK-RV32-F-NEXT: fsw ft1, 120(sp)
114 ; CHECK-RV32-F-NEXT: fsw ft2, 116(sp)
115 ; CHECK-RV32-F-NEXT: fsw ft3, 112(sp)
116 ; CHECK-RV32-F-NEXT: fsw ft4, 108(sp)
117 ; CHECK-RV32-F-NEXT: fsw ft5, 104(sp)
118 ; CHECK-RV32-F-NEXT: fsw ft6, 100(sp)
119 ; CHECK-RV32-F-NEXT: fsw ft7, 96(sp)
120 ; CHECK-RV32-F-NEXT: fsw fa0, 92(sp)
121 ; CHECK-RV32-F-NEXT: fsw fa1, 88(sp)
[all …]
|
| D | interrupt-attr-nocall.ll | 214 ; CHECK-RV32IF-NEXT: fsw ft0, 8(sp)
215 ; CHECK-RV32IF-NEXT: fsw ft1, 4(sp)
222 ; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
241 ; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
312 ; CHECK-RV32IF-NEXT: fsw ft0, 16(sp)
313 ; CHECK-RV32IF-NEXT: fsw ft1, 12(sp)
321 ; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
345 ; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
432 ; CHECK-RV32IF-NEXT: fsw ft0, 124(sp)
433 ; CHECK-RV32IF-NEXT: fsw ft1, 120(sp)
[all …]
|
| D | float-mem.ll | 32 define void @fsw(float *%a, float %b, float %c) nounwind {
35 ; RV32IF-LABEL: fsw:
40 ; RV32IF-NEXT: fsw ft0, 0(a0)
41 ; RV32IF-NEXT: fsw ft0, 32(a0)
44 ; RV64IF-LABEL: fsw:
49 ; RV64IF-NEXT: fsw ft0, 0(a0)
50 ; RV64IF-NEXT: fsw ft0, 32(a0)
72 ; RV32IF-NEXT: fsw ft0, %lo(G)(a0)
76 ; RV32IF-NEXT: fsw ft0, 36(a1)
86 ; RV64IF-NEXT: fsw ft0, %lo(G)(a0)
[all …]
|
| D | inline-asm-clobbers.ll | 27 ; RV32I-NOT: fsw fs0, {{[0-9]+}}(sp)
33 ; RV64I-NOT: fsw fs0, {{[0-9]+}}(sp)
39 ; RV32IF-NEXT: fsw fs0, {{[0-9]+}}(sp)
40 ; RV32IF-NEXT: fsw fs1, {{[0-9]+}}(sp)
45 ; RV64IF-NEXT: fsw fs0, {{[0-9]+}}(sp)
46 ; RV64IF-NEXT: fsw fs1, {{[0-9]+}}(sp)
|
| D | inline-asm-f-abi-names.ll | 344 ; RV32IF-NEXT: fsw fs0, 12(sp)
356 ; RV64IF-NEXT: fsw fs0, 12(sp)
373 ; RV32IF-NEXT: fsw fs0, 12(sp)
385 ; RV64IF-NEXT: fsw fs0, 12(sp)
402 ; RV32IF-NEXT: fsw fs1, 12(sp)
414 ; RV64IF-NEXT: fsw fs1, 12(sp)
431 ; RV32IF-NEXT: fsw fs1, 12(sp)
443 ; RV64IF-NEXT: fsw fs1, 12(sp)
776 ; RV32IF-NEXT: fsw fs2, 12(sp)
788 ; RV64IF-NEXT: fsw fs2, 12(sp)
[all …]
|
| D | calling-conv-rv32f-ilp32.ll | 63 ; RV32IF-NEXT: fsw ft0, 4(sp)
68 ; RV32IF-NEXT: fsw ft2, 0(sp)
|
| D | half-mem.ll | 122 ; RV32IZFH-NEXT: fsw fs0, 8(sp)
137 ; RV64IZFH-NEXT: fsw fs0, 4(sp)
|
| D | double-mem.ll | 250 ; RV32IFD-NEXT: fsw ft0, 0(a0)
258 ; RV64IFD-NEXT: fsw ft0, 0(a0)
|
| /external/llvm-project/llvm/test/MC/RISCV/ |
| D | compress-rv32f.s | 18 fsw ft0, 124(sp) label
20 # CHECK-ALIAS: fsw ft0, 124(sp)
28 fsw fs0, 124(s0) label
30 # CHECK-ALIAS: fsw fs0, 124(s0)
31 # CHECK-INST: c.fsw fs0, 124(s0)
|
| D | rv32f-valid.s | 31 # CHECK-ASM-AND-OBJ: fsw ft6, 2047(s4)
33 fsw f6, 2047(s4) label
34 # CHECK-ASM-AND-OBJ: fsw ft7, -2048(s5)
36 fsw f7, -2048(s5) label
37 # CHECK-ASM-AND-OBJ: fsw fs0, -2048(s6)
39 fsw f8, %lo(2048)(s6) label
40 # CHECK-ASM-AND-OBJ: fsw fs1, 999(s7)
42 fsw f9, 999(s7) label
|
| D | rvf-pseudos.s | 11 # CHECK: fsw fa2, %pcrel_lo(.Lpcrel_hi1)(a3)
12 fsw fa2, a_symbol, a3 label
|
| D | rv32fc-aliases-valid.s | 9 # CHECK-EXPAND: c.fsw fs0, 0(s1)
10 c.fsw f8, (x9)
|
| D | rv32f-invalid.s | 6 fsw ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel… label
10 fsw ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction label
|
| D | rvf-aliases-valid.s | 27 # TODO fsw
112 # CHECK-INST: fsw ft0, 0(a0)
113 # CHECK-ALIAS: fsw ft0, 0(a0)
114 fsw f0, (x10) label
|
| D | rv32fc-valid.s | 38 # CHECK-ASM-AND-OBJ: c.fsw fa2, 124(a1)
43 c.fsw fa2, 124(a1)
|
| D | rv32fc-invalid.s | 12 c.fsw fs1, 128(sp) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 4 bytes in the r…
|
| D | rv32zfh-invalid.s | 11 fsw ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction label
|
| /external/llvm-project/lldb/source/Plugins/Process/Utility/ |
| D | RegisterContextDarwin_i386.cpp | 293 {DEFINE_FPU_UINT(fsw),
626 value = fpu.fsw; in ReadRegister()
743 fpu.fsw = value.GetAsUInt16(); in WriteRegister()
|
| D | RegisterContextDarwin_x86_64.cpp | 347 {DEFINE_FPU_UINT(fsw),
677 value = fpu.fsw; in ReadRegister()
803 fpu.fsw = value.GetAsUInt16(); in WriteRegister()
|
| D | RegisterContextDarwin_x86_64.h | 83 uint16_t fsw; // "fstat" member
|
| D | RegisterContextDarwin_i386.h | 78 uint16_t fsw; member
|
| /external/crosvm/hypervisor/src/kvm/ |
| D | x86_64.rs | 1095 fsw: r.fsw, in from()
1111 fsw: r.fsw, in from()
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoF.td | 116 "fsw", "$rs2, ${imm12}(${rs1})">,
238 def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
282 def PseudoFSW : PseudoStore<"fsw", FPR32>;
|