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/external/mesa3d/src/intel/tools/tests/gen8/
Dmad.asm7 mad(16) g15<1>F -g2.6<0,1,0>F g13<4,4,1>F g1.0<0,1,0>F { align16 1H };
8 mad(8) g124<1>F -g15.0<0,1,0>F g14<4,4,1>F g15.1<0,1,0>F { align16 1Q };
9 mad(8) g124<1>F g15.0<0,1,0>F g14<4,4,1>F -g15.1<0,1,0>F { align16 1Q };
10 mad.le.f0.0(8) g9<1>F g3<4,4,1>F g4.2<0,1,0>F g15<4,4,1>F { align16 1Q };
11 mad.le.f0.0(16) g15<1>F g4<4,4,1>F g6.2<0,1,0>F g24<4,4,1>F { align16 1H };
18 mad(8) g15<1>F g2.1<0,1,0>F g11<4,4,1>F (abs)g5.6<0,1,0>F { align16 1Q };
43 mad.nz.f0.0(16) g15<1>F -g33.0<0,1,0>F g9<4,4,1>F g17<4,4,1>F { align16 1H };
Dcsel.asm1 csel.nz(8) g15<1>F g11<4,4,1>F (abs)g11<4,4,1>F g11<4,4,1>F { align16 1Q };
9 csel.le(16) g15<1>F g58<4,4,1>F (abs)g73<4,4,1>F g73<4,4,1>F { align16 1H };
Dfbh.asm1 fbh(8) g15<1>D g35<8,8,1>D { align1 1Q };
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dmad.asm6 mad.le.f0.0(8) g9<1>F g3<4,4,1>F g4.2<0,1,0>F g15<4,4,1>F { align16 1Q };
7 mad.le.f0.0(16) g15<1>F g4<4,4,1>F g6.2<0,1,0>F g24<4,4,1>F { align16 1H };
8 mad(8) g32<1>F g31<4,4,1>F g2.3<0,1,0>F -g15<4,4,1>F { align16 1Q };
14 mad.ge.f0.0(8) g16<1>.xF g4<4,4,1>.xF g15<4,4,1>.xF -g1.4<0,1,0>F { align16 1Q };
36 mad(16) g15<1>F g35.2<0,1,0>F -g35.3<0,1,0>F (abs)g2.0<0,1,0>F { align16 1H };
39 mad.nz.f0.0(16) g15<1>F -g33.0<0,1,0>F g9<4,4,1>F g17<4,4,1>F { align16 1H };
Dadd.asm2 add(16) g120<1>F g15<8,8,1>D 1D { align1 1H };
13 add(8) g17<1>D g15<8,8,1>D -g7.3<0,1,0>D { align1 1Q };
59 add(16) g17<1>F -g15<4>.xyxyF g15<4>.zwzwF { align16 1H };
65 add.nz.f0.0(8) g15<1>.xD g1<4>.zD g1<4>.xD { align16 1Q };
Dmach.asm9 mach(8) g15<1>D g12<4>D g14<4>D { align16 1Q AccWrEnable };
11 mach(8) g15<1>.xD g5<4>.xD 1431655766D { align16 1Q AccWrEnable };
Dor.asm13 or(1) a0<1>UD a0<0,1,0>UD g15<0,1,0>UD { align1 WE_all 1N };
22 or(16) g16<1>UW g14<16,16,1>UW g15<16,16,1>UW { align1 1H };
Dmov.asm9 mov(16) g122<1>F -g15<8,8,1>D { align1 1H };
27 mov(8) g15<1>.xUD g5<0>.wUD { align16 1Q };
35 mov(8) g17<1>F -g15<4>D { align16 1Q };
36 mov(8) g15<1>F g14<4>UD { align16 1Q };
95 mov(16) g15<1>UD g11<8,8,1>F { align1 1H };
96 mov(16) g19<1>UD g15<16,8,2>UW { align1 1H };
166 mov(16) g15<1>UD 1043072D { align1 1H };
Dmath.asm7 math sqrt(16) g15<1>F g13<8,8,1>F null<8,8,1>F { align1 1H };
19 math exp(8) g16<1>.xF g15<4>.xF null<4>F { align16 1Q };
20 math log(8) g15<1>.xF g14<4>.xF null<4>F { align16 1Q };
Dmul.asm16 mul.sat(8) g19<1>.xyzF g15<4>.xyzzF g18<4>.xF { align16 1Q };
29 mul(8) g115<1>.xF g15<4>.xF 0x40a66666F /* 5.2F */ { align16 NoDDClr,NoDDChk 1…
42 mul(16) g15<1>UW g14<16,16,1>UW 0x0808UW { align1 1H };
Dfbh.asm1 fbh(8) g16<1>D g15<4>D { align16 1Q };
/external/igt-gpu-tools/assembler/doc/examples/
Dpacked_yuv_wm.g4a100 * Y is g14, g15.
131 add (8) g15<1>F g15<8,8,1>F -0.0627451F { align1 };
134 mul (8) g15<1>F g15<8,8,1>F 1.164F { align1 };
136 mac.sat (8) m6<1>F g15<8,8,1>F 1F { align1 };
139 mac.sat (8) m7<1>F g15<8,8,1>F 1F { align1 };
141 mac.sat (8) m8<1>F g15<8,8,1>F 1F { align1 };
/external/mesa3d/src/intel/tools/tests/gen6/
Dmath.asm3 math pow(8) g16<1>F g15<8,8,1>F g14<8,8,1>F { align1 1Q };
7 math sqrt(8) g16<1>F g15<8,8,1>F null<8,8,1>F { align1 1Q };
25 math intmod(8) g75<1>UD g73<8,8,1>UD g15<8,8,1>UD { align1 2Q };
Dadd.asm38 add(8) g15<1>.yD g1<0>.xD 49D { align16 NoDDClr 1Q };
39 add(8) g15<1>.zD g1<0>.xD 50D { align16 NoDDClr,NoDDChk 1Q };
41 add(8) g15<1>.wD g1<0>.xD 51D { align16 NoDDChk 1Q };
54 add(8) g15<1>.wF g2<0>.xF 0x40400000F /* 3F */ { align16 NoDDClr,NoDDChk 1Q …
67 add.sat(8) m4<1>.xF -g15<4>.xF 0x3f800000F /* 1F */ { align16 NoDDClr 1Q };
Dsel.asm17 (+f0.0) sel(16) m1<1>UD g15<8,8,1>UD g21<8,8,1>UD { align1 1H };
24 (+f0.0.any4h) sel(8) g15<1>UD g14<4>UD g4<4>UD { align16 1Q };
29 sel.l(16) g15<1>F g2.3<0,1,0>F g2.2<0,1,0>F { align1 1H };
41 (-f0.0) sel(8) g15<1>F (abs)g14<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q };
/external/mesa3d/src/intel/tools/tests/gen9/
Dmad.asm7 mad(16) g29<1>F -g33.0<0,1,0>F g25<4,4,1>F g15<4,4,1>F { align16 1H };
11 mad(8) g32<1>F g31<4,4,1>F g2.3<0,1,0>F -g15<4,4,1>F { align16 1Q };
18 mad(8) g15<1>F g2.1<0,1,0>F g11<4,4,1>F (abs)g5.6<0,1,0>F { align16 1Q };
43 mad.nz.f0.0(16) g15<1>F -g33.0<0,1,0>F g9<4,4,1>F g17<4,4,1>F { align16 1H };
Dcsel.asm1 csel.nz(8) g15<1>F g11<4,4,1>F (abs)g11<4,4,1>F g11<4,4,1>F { align16 1Q };
9 csel.le(16) g15<1>F g58<4,4,1>F (abs)g73<4,4,1>F g73<4,4,1>F { align16 1H };
Dfbh.asm1 fbh(8) g15<1>D g35<8,8,1>D { align1 1Q };
Dmov.asm42 mov(8) g15<1>F g11<8,8,1>UD { align1 1Q };
72 mov(16) g15<1>UD g11<8,8,1>F { align1 1H };
73 mov(16) g19<1>UD g15<16,8,2>UW { align1 1H };
95 mov(16) g124<1>UD g15<8,8,1>UD { align1 2H };
131 mov(16) g35<1>F g15<16,8,2>W { align1 1H };
/external/clang/test/CodeGen/
Dconst-init.c91 int g15 = (int) (char) ((void*) 0 + 255); variable
97 int *g17 = (int *) ((long) &g15);
/external/llvm-project/clang/test/CodeGen/
Dconst-init.c91 int g15 = (int) (char) ((void*) 0 + 255); variable
97 int *g17 = (int *) ((long) &g15);
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dppc64-fastcc.ll7 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
15 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
23 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
31 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
39 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
47 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
55 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
63 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
71 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
79 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dppc64-fastcc.ll7 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
15 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
23 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
31 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
39 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
47 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
55 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
63 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
71 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
79 …, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x …
[all …]
/external/mesa3d/src/intel/tools/tests/gen7/
Dmul.asm9 mul.sat(8) g19<1>.xyzF g15<4>.xyzzF g18<4>.xF { align16 1Q };
30 mul(8) g115<1>.xF g15<4>.xF 0x40a66666F /* 5.2F */ { align16 NoDDClr,NoDDChk 1…
45 mul(1) g3<1>UD g15<0,1,0>UD 0x0101UW { align1 WE_all 1N };
Dfbh.asm1 fbh(8) g16<1>D g15<4>D { align16 1Q };

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