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/external/mesa3d/src/intel/tools/tests/gen7/
Dbfi2.asm1 bfi2(8) g23<1>UD g22<4,4,1>UD g18<4,4,1>UD g17<4,4,1>UD { align16 1Q };
2 bfi2(8) g19<1>UD g17<4,4,1>UD g54<4,4,1>UD g7<4,4,1>UD { align16 2Q };
Dsel.asm11 sel.ge(16) g17<1>F g3<8,8,1>F 0x0F /* 0F */ { align1 1H };
27 (+f0.0.x) sel(8) g17<1>.xF g5.4<0>.zF -g5.4<0>.zF { align16 1Q };
32 (+f0.0.any4h) sel(8) g17<1>.xUD g8<4>.xUD 0x00000001UD { align16 1Q };
48 (+f1.0) sel(4) g17<1>.xUD g15.4<4>.xUD g15<4>.xUD { align16 WE_all 1N };
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dbfi2.asm1 bfi2(8) g23<1>UD g22<4,4,1>UD g18<4,4,1>UD g17<4,4,1>UD { align16 1Q };
2 bfi2(8) g19<1>UD g17<4,4,1>UD g52<4,4,1>UD g7<4,4,1>UD { align16 2Q };
Dmul.asm2 mul(8) g18<1>F g17<4>F 0x3f000000F /* 0.5F */ { align16 1Q };
6 mul(8) acc0<1>UD g17<8,8,1>UD 0xaaaaaaabUD { align1 1Q };
7 mul(8) acc0<1>D g17<8,8,1>D 1431655766D { align1 1Q };
43 mul.sat(8) g11<1>F g17<8,8,1>F 0x40800000F /* 4F */ { align1 1Q };
44 mul.sat(16) g21<1>F g17<8,8,1>F 0x40800000F /* 4F */ { align1 1H };
Dmach.asm1 mach(8) g19<1>UD g17<8,8,1>UD 0xaaaaaaabUD { align1 1Q AccWrEnable };
2 mach(8) g10<1>D g17<8,8,1>D 1431655766D { align1 1Q AccWrEnable };
Dadd.asm6 add(8) g17<1>F g6<0>F g7.4<0>F { align16 1Q };
13 add(8) g17<1>D g15<8,8,1>D -g7.3<0,1,0>D { align1 1Q };
41 add(8) g17<1>UD g29<0,1,0>UD g26.2<1,4,0>UW { align1 2Q };
59 add(16) g17<1>F -g15<4>.xyxyF g15<4>.zwzwF { align16 1H };
Dsel.asm19 (+f0.0) sel(8) g8<1>.xyUD g17<4>.xyyyUD 0x3f000000UD { align16 1Q };
43 sel.ge(16) g29<1>F g27<8,8,1>F (abs)g17<8,8,1>F { align1 1H };
48 (+f0.0.x) sel(8) g17<1>.xF g5.4<0>.zF -g5.4<0>.zF { align16 1Q };
51 (+f0.0.any4h) sel(8) g17<1>.xUD g8<4>.xUD 0x00000001UD { align16 1Q };
/external/mesa3d/src/intel/tools/tests/gen8/
Dmach.asm1 mach(8) g19<1>UD g17<8,8,1>UD 0xaaaaaaabUD { align1 1Q AccWrEnable };
2 mach(8) g23<1>D g17<8,8,1>D 1431655766D { align1 1Q AccWrEnable };
Drndd.asm1 rndd(8) g22<1>F g17<0,1,0>F { align1 1Q };
3 rndd.z.f0.0(8) null<1>F g17<8,8,1>F { align1 1Q };
Dmul.asm5 mul(8) acc0<1>UD g17<8,8,1>UD 0xaaabUW { align1 1Q };
6 mul(8) acc0<1>D g17<8,8,1>D 0x5556UW { align1 1Q };
14 mul.sat(8) g17<1>F g4<8,8,1>F g16<8,8,1>F { align1 1Q };
Dor.asm14 (+f0.0) or(8) g17.1<2>UD g17.1<8,4,2>UD 0x3ff00000UD { align1 2Q };
/external/mesa3d/src/intel/tools/tests/gen9/
Dmach.asm1 mach(8) g19<1>UD g17<8,8,1>UD 0xaaaaaaabUD { align1 1Q AccWrEnable };
2 mach(8) g23<1>D g17<8,8,1>D 1431655766D { align1 1Q AccWrEnable };
Drndd.asm1 rndd(8) g22<1>F g17<0,1,0>F { align1 1Q };
3 rndd.z.f0.0(8) null<1>F g17<8,8,1>F { align1 1Q };
Dor.asm14 (+f0.0) or(8) g17.1<2>UD g17.1<8,4,2>UD 0x3ff00000UD { align1 2Q };
23 or.z.f0.0(16) null<1>UD g17<8,8,1>UD g19<8,8,1>UD { align1 1H };
Dmul.asm5 mul(8) acc0<1>UD g17<8,8,1>UD 0xaaabUW { align1 1Q };
6 mul(8) acc0<1>D g17<8,8,1>D 0x5556UW { align1 1Q };
14 mul.sat(8) g17<1>F g4<8,8,1>F g16<8,8,1>F { align1 1Q };
/external/mesa3d/src/intel/tools/tests/gen6/
Dxor.asm1 xor(8) g17<1>D g17<4>D g2<0>D { align16 1Q };
Dmad.asm2 mad(8) g17<1>F g6.7<0,1,0>F g6.3<0,1,0>F g13<4,4,1>F { align16 2Q };
27 mad(8) g3<1>.yF g17<4,4,1>.yF g6<4,4,1>.xF g19<4,4,1>.xF { align16 NoDDClr 1Q …
28 mad(8) g2<1>F -g2<4,4,1>F (abs)g8<4,4,1>F g17.0<0,1,0>F { align16 1Q };
29 mad(8) g13<1>F -g5<4,4,1>F (abs)g3<4,4,1>F g17.0<0,1,0>F { align16 2Q };
41 mad.nz.f0.0(8) g19<1>F -g30.0<0,1,0>F g10<4,4,1>F g17<4,4,1>F { align16 2Q };
Dor.asm7 or.nz.f0.0(8) null<1>.xUD g17<4>.xUD g16<4>.xUD { align16 1Q };
8 or.nz.f0.0(8) null<1>UD g16<8,8,1>UD g17<8,8,1>UD { align1 1Q };
/external/mesa3d/src/intel/tools/tests/gen4.5/
Dor.asm6 (+f0.0) or(8) g17<1>.xUD g17<4>.xUD 0x3f800000UD { align16 };
/external/mesa3d/src/intel/tools/tests/gen5/
Dor.asm6 (+f0.0) or(8) g17<1>.xUD g17<4>.xUD 0x3f800000UD { align16 };
Ddp3.asm3 dp3(8) g25<1>.xF g17<4>.xyzzF g3<0>.xyzzF { align16 };
8 dp3.le.f0.0(8) g18<1>.xF g17<4>.xyzzF g3.4<0>.xyzzF { align16 };
/external/llvm-project/clang/test/Sema/
Dprivate-extern.c77 extern int g17;
78 int g17 = 0; variable
/external/clang/test/Sema/
Dprivate-extern.c77 extern int g17;
78 int g17 = 0; variable
/external/llvm-project/llvm/test/MC/Hexagon/
Dguest.s36 r1:0=g17:16
37 # CHECK: { r1:0 = g17:16 }
/external/igt-gpu-tools/assembler/doc/examples/
Dpacked_yuv_wm.g4a102 * Cb is g16, g17.
133 add (8) g17<1>F g17<8,8,1>F -0.501961F { align1 };
138 mac (8) null g17<8,8,1>F -0.392F { align1 };
140 mul (8) null g17<8,8,1>F 2.017F { align1 };

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