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/external/mesa3d/src/mesa/sparc/
Dsparc_clip.S100 ld [%i0 + 0x08], %g4 ! LSU Group
104 addcc %g4, %g4, %g4 ! IEU1 Group
106 subcc %g5, %g4, %g0 ! IEU1 Group
107 ld [%i0 + 0x04], %g4 ! LSU Group
109 addcc %g4, %g4, %g4 ! IEU1 Group
111 subcc %g5, %g4, %g0 ! IEU1 Group
112 ld [%i0 + 0x00], %g4 ! LSU Group
114 addcc %g4, %g4, %g4 ! IEU1 Group
116 subcc %g5, %g4, %g0 ! IEU1 Group
122 sll %g3, 8, %g4 ! IEU1 Group
[all …]
/external/mesa3d/src/intel/tools/tests/gen5/
Dsel.asm4 (-f0.0) sel(16) g4<1>UD g6<8,8,1>UD 0x00000000UD { align1 compr };
5 (+f0.0) sel(8) g4<1>.yF g5<4>.xF 0x0F /* 0F */ { align16 };
6 (-f0.0.z) sel(8) g4<1>.zUD g6<4>.xUD 0x00000000UD { align16 };
7 (+f0.0) sel(8) g2<1>F (abs)g4<8,8,1>F (abs)g3<8,8,1>F { align1 };
8 (+f0.0) sel(16) g4<1>F (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
10 (+f0.0) sel(8) m3<1>UD g4<8,8,1>UD g2<8,8,1>UD { align1 };
11 (+f0.0) sel(16) g4<1>UD g12<8,8,1>UD g14<8,8,1>UD { align1 compr };
12 (+f0.0) sel(16) m3<1>UD g10<8,8,1>UD g4<8,8,1>UD { align1 compr4 };
15 (+f0.0) sel(16) m11<1>UD g4<8,8,1>UD 0x3f000000UD { align1 compr };
19 (+f0.0) sel(8) m4<1>F g3<8,8,1>F g4<8,8,1>F { align1 };
[all …]
Dmov.asm3 mov.sat(8) m5<1>F g4<4>F { align16 };
6 mov(8) m3<1>F g4.3<0,1,0>F { align1 };
7 mov(16) m3<1>F g4.3<0,1,0>F { align1 compr4 };
11 mov(16) g12<1>F g4<8,8,1>UW { align1 compr };
12 mov(16) g4<1>D g12<8,8,1>F { align1 compr };
13 mov(16) g12<1>F g4<8,8,1>D { align1 compr };
24 mov(8) g4<1>.xyD g2<4>.xyyyD { align16 };
30 mov(16) m2<1>D g4<8,8,1>F { align1 compr };
38 mov(16) m3<1>UD g4<8,8,1>UD { align1 compr4 };
46 mov(8) g3<1>.yF g4<4>.xD { align16 NoDDClr,NoDDChk };
[all …]
Dadd.asm6 add(16) g4<1>F g10<8,8,1>F g6.7<0,1,0>F { align1 compr };
8 add(8) g4<1>.xD g5<4>.xD g4<4>.xD { align16 };
14 add(8) m3<1>F g4<8,8,1>F g2.1<0,1,0>F { align1 };
17 add.le.f0.0(8) g3<1>F g3<8,8,1>F g4<8,8,1>F { align1 };
18 add.le.f0.0(16) g6<1>F g8<8,8,1>F g4<8,8,1>F { align1 compr };
23 add.sat(16) g6<1>F g4<8,8,1>F g2.1<0,1,0>F { align1 compr };
25 add(16) g12<1>D g4<8,8,1>D -g9.3<0,1,0>D { align1 compr };
29 add(8) g3.1<2>UW g3.1<16,8,2>UW g4<16,8,2>UW { align1 };
30 add(16) g4.1<2>UW g4.1<16,8,2>UW g6<16,8,2>UW { align1 compr };
31 add(8) g4<1>.xyF g4<4>.xyyyF 0xbf800000F /* -1F */ { align16 NoDDClr };
[all …]
Dshl.asm1 shl(8) g4<1>.xD g1<0>.yD 0x00000004UD { align16 };
2 shl(8) g4<1>D g3<8,8,1>D 0x00000001UD { align1 };
3 shl(16) g6<1>D g4<8,8,1>D 0x00000001UD { align1 compr };
5 shl(8) m14<1>D g4<0,1,0>D 0x00000004UD { align1 };
6 shl(16) m14<1>D g4<0,1,0>D 0x00000004UD { align1 compr };
7 shl(8) g5<1>D g3<4>D g4<4>UD { align16 };
Dcmp.asm9 cmp.ge.f0.0(8) g6<1>F g4<8,8,1>F 0x26901d7dF /* 1e-15F */ { align1 };
11 cmp.ge.f0.0(8) null<1>F (abs)g4<8,8,1>F (abs)g3<8,8,1>F { align1 };
17 cmp.z.f0.0(8) g9<1>.xD g4<4>.xD g1<0>.xD { align16 };
22 cmp.z.f0.0(8) null<1>F g4.1<0,1,0>F 0x3f800000F /* 1F */ { align1 };
23 cmp.z.f0.0(16) null<1>F g4.1<0,1,0>F 0x3f800000F /* 1F */ { align1 compr };
26 cmp.z.f0.0(16) g4<1>D g8<8,8,1>D g2.5<0,1,0>D { align1 compr };
36 cmp.le.f0.0(16) null<1>F g4<8,8,1>F 0x3f000000F /* 0.5F */ { align1 compr };
37 cmp.le.f0.0(16) g20<1>F g4<8,8,1>F 0x461c3f9aF /* 9999.9F */ { align1 compr };
42 cmp.g.f0.0(8) g4<1>F g3<4>F 0x3f000000F /* 0.5F */ { align16 };
47 cmp.g.f0.0(16) g6<1>F (abs)g4<8,8,1>F 0x3a83126fF /* 0.001F */ { align1 compr };
[all …]
Ddp3.asm5 dp3(8) g19<1>.yF g3<0>.xyzzF g4<0>.xyzzF { align16 NoDDClr,NoDDChk };
6 dp3(8) g19<1>.zF g3<0>.xyzzF g4.4<0>.xyzzF { align16 NoDDChk };
7 dp3(8) m5<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 };
9 dp3.sat(8) g4<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 };
/external/mesa3d/src/intel/tools/tests/gen4.5/
Dadd.asm4 add(16) g4<1>F g18<8,8,1>F g6<8,8,1>F { align1 compr };
7 add(8) g4<1>.xD g5<4>.xD g4<4>.xD { align16 };
12 add.le.f0.0(16) g6<1>F g8<8,8,1>F g4<8,8,1>F { align1 compr };
13 add(16) m3<1>F g4<8,8,1>F g12<8,8,1>F { align1 compr4 };
14 add(8) a0<1>UW g4<16,8,2>UW 0x0040UW { align1 };
19 add(16) m14<1>D g4<8,8,1>D 12D { align1 compr };
20 add.sat(16) g6<1>F g4<8,8,1>F g2.1<0,1,0>F { align1 compr };
24 add(16) g4<1>D g2<0,1,0>D -g2.2<0,1,0>D { align1 compr };
29 add(16) g4.1<2>UW g4.1<16,8,2>UW g6<16,8,2>UW { align1 compr };
30 add.ge.f0.0(16) g4<1>F -g6<8,8,1>F 0x3f800000F /* 1F */ { align1 compr };
[all …]
Dcmp.asm3 cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
4 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
5 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
6 cmp.ge.f0.0(16) g10<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
7 cmp.z.f0.0(8) g10<1>.xD g4<0>.xD 0D { align16 };
18 cmp.z.f0.0(16) g4<1>F g2.1<0,1,0>F 0x41000000F /* 8F */ { align1 compr };
24 cmp.nz.f0.0(16) g4<1>F g6<8,8,1>F g2.2<0,1,0>F { align1 compr };
30 cmp.z.f0.0(16) null<1>F g4.1<0,1,0>F 0x3f800000F /* 1F */ { align1 compr };
31 cmp.ge.f0.0(16) g4<1>D g2<0,1,0>D 1D { align1 compr };
32 cmp.nz.f0.0(16) g4<1>D g2.1<0,1,0>D 0D { align1 compr };
[all …]
Dmov.asm3 mov.sat(8) m5<1>F g4<4>F { align16 };
9 mov(16) m4<1>F g4<8,8,1>F { align1 compr4 };
14 mov(16) m3<1>F g4<8,8,1>D { align1 compr4 };
18 mov(16) g12<1>F g4<8,8,1>UW { align1 compr };
19 mov(16) g4<1>D g12<8,8,1>F { align1 compr };
20 mov(16) g12<1>F g4<8,8,1>D { align1 compr };
22 mov(8) g7<1>.xD g4<0>.yD { align16 };
24 mov(8) g7<1>.yD g4<0>.yD { align16 NoDDChk };
28 mov(16) m2<1>D g4<8,8,1>F { align1 compr };
46 mov(16) m3<1>UD g4<8,8,1>UD { align1 compr4 };
[all …]
Dsel.asm7 (-f0.0) sel(16) g4<1>UD g6<8,8,1>UD 0x00000000UD { align1 compr };
10 (+f0.0) sel(16) g4<1>F (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
19 (+f0.0) sel(16) m4<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr4 };
20 (-f0.0.y) sel(8) g3<1>.yUD g4<4>.xUD 0x00000000UD { align16 };
26 (-f0.0) sel(8) g4<1>.xyzF (abs)g4<4>.xyzzF 0x3f800000F /* 1F */ { align16 };
27 (+f0.0.x) sel(8) g4<1>.xD -g4<4>.xD 0D { align16 };
28 (+f0.0) sel(16) g4<1>D -g6<8,8,1>D -1D { align1 compr };
30 (+f0.0) sel(16) m3<1>F g4<8,8,1>F 0x3f800000F /* 1F */ { align1 compr4 };
Dsend.asm17 send(16) 1 g4<1>UW g0<8,8,1>UW 0x02780001
19 send(16) 1 g4<1>UW g0<8,8,1>UW 0x02580001
27 send(16) 1 g4<1>UW g0<8,8,1>UW 0x02983001
35 send(8) 2 g6<1>F g4<8,8,1>F 0x0121000a
39 send(16) 2 g6<1>F g4<8,8,1>F 0x01110007
43 send(16) 2 g4<1>F g2.4<0,1,0>F 0x01110081
45 send(16) 1 g4<1>UW g0<8,8,1>UW 0x02980001
65 send(16) 2 g6<1>F g4<8,8,1>F 0x01110003
67 send(16) 1 g4<1>UW g0<8,8,1>UW 0x02983005
83 send(8) 2 g4<1>D g2.4<0,1,0>D 0x0121009c
[all …]
Ddp3.asm5 dp3(8) g19<1>.yF g3<0>.xyzzF g4<0>.xyzzF { align16 NoDDClr,NoDDChk };
6 dp3(8) g19<1>.zF g3<0>.xyzzF g4.4<0>.xyzzF { align16 NoDDChk };
7 dp3(8) m5<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 };
9 dp3.sat(8) g4<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 };
/external/mesa3d/src/intel/tools/tests/gen4/
Dadd.asm3 add(16) g4<1>F g18<8,8,1>F g6<8,8,1>F { align1 compr };
6 add(8) g4<1>.xD g5<4>.xD g4<4>.xD { align16 };
11 add.le.f0.0(16) g6<1>F g8<8,8,1>F g4<8,8,1>F { align1 compr };
12 add(8) a0<1>UW g4<16,8,2>UW 0x0040UW { align1 };
16 add(16) m14<1>D g4<8,8,1>D 12D { align1 compr };
17 add.sat(16) g6<1>F g4<8,8,1>F g2.1<0,1,0>F { align1 compr };
22 add(16) g4<1>D g2<0,1,0>D -g2.2<0,1,0>D { align1 compr };
27 add(16) g4.1<2>UW g4.1<16,8,2>UW g6<16,8,2>UW { align1 compr };
28 add.ge.f0.0(16) g4<1>F -g6<8,8,1>F 0x3f800000F /* 1F */ { align1 compr };
29 add(8) g4<1>.xyF g4<4>.xyyyF 0xbf800000F /* -1F */ { align16 NoDDClr };
[all …]
Dcmp.asm4 cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
5 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
6 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
7 cmp.ge.f0.0(16) g10<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
8 cmp.z.f0.0(8) g10<1>.xD g4<0>.xD 0D { align16 };
21 cmp.z.f0.0(16) g4<1>F g2.1<0,1,0>F 0x41000000F /* 8F */ { align1 compr };
27 cmp.nz.f0.0(16) g4<1>F g6<8,8,1>F g2.2<0,1,0>F { align1 compr };
32 cmp.z.f0.0(16) null<1>F g4.1<0,1,0>F 0x3f800000F /* 1F */ { align1 compr };
33 cmp.ge.f0.0(16) g4<1>D g2<0,1,0>D 1D { align1 compr };
34 cmp.nz.f0.0(16) g4<1>D g2.1<0,1,0>D 0D { align1 compr };
[all …]
Dmov.asm5 mov.sat(8) m5<1>F g4<4>F { align16 };
16 mov(16) g8<1>F g4<8,8,1>D { align1 compr };
21 mov(16) g12<1>F g4<8,8,1>UW { align1 compr };
22 mov(16) g4<1>D g12<8,8,1>F { align1 compr };
26 mov(8) g7<1>.xD g4<0>.yD { align16 };
28 mov(8) g7<1>.yD g4<0>.yD { align16 NoDDChk };
32 mov(16) m2<1>D g4<8,8,1>F { align1 compr };
46 mov(8) m3<1>UD g4<8,8,1>UD { align1 };
47 mov(8) m7<1>UD g4<8,8,1>UD { align1 sechalf };
56 mov(8) g3<1>.yF g4<4>.xD { align16 NoDDClr,NoDDChk };
[all …]
Dsel.asm7 (-f0.0) sel(16) g4<1>UD g6<8,8,1>UD 0x00000000UD { align1 compr };
8 (+f0.0) sel(8) g4<1>.yF g5<4>.xF 0x0F /* 0F */ { align16 };
9 (-f0.0.z) sel(8) g4<1>.zUD g6<4>.xUD 0x00000000UD { align16 };
12 (+f0.0) sel(16) g4<1>F (abs)g14<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
18 (-f0.0.y) sel(8) g3<1>.yUD g4<4>.xUD 0x00000000UD { align16 };
24 (-f0.0) sel(8) g4<1>.xyzF (abs)g4<4>.xyzzF 0x3f800000F /* 1F */ { align16 };
25 (+f0.0.x) sel(8) g4<1>.xD -g4<4>.xD 0D { align16 };
26 (+f0.0) sel(16) g4<1>D -g6<8,8,1>D -1D { align1 compr };
Ddp3.asm5 dp3(8) g19<1>.yF g3<0>.xyzzF g4<0>.xyzzF { align16 NoDDClr,NoDDChk };
6 dp3(8) g19<1>.zF g3<0>.xyzzF g4.4<0>.xyzzF { align16 NoDDChk };
7 dp3(8) m5<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 };
9 dp3.sat(8) g4<1>.xF g4<4>.xyzzF g5<4>.xyzzF { align16 };
Dsend.asm17 send(16) 1 g4<1>UW g0<8,8,1>UW 0x02780001
19 send(16) 1 g4<1>UW g0<8,8,1>UW 0x02580001
27 send(16) 1 g4<1>UW g0<8,8,1>UW 0x0298c001
35 send(8) 2 g6<1>F g4<8,8,1>F 0x0121000a
39 send(8) 2 g6<1>F g4<8,8,1>F 0x01110007
43 send(8) 2 g4<1>F g2.4<0,1,0>F 0x01110081
45 send(16) 1 g4<1>UW g0<8,8,1>UW 0x02980001
47 send(16) 1 g4<1>UW g0<8,8,1>UW 0x0298e001
67 send(8) 2 g6<1>F g4<8,8,1>F 0x01110003
69 send(8) 2 g4<1>D g2.4<0,1,0>D 0x0121009c
[all …]
/external/llvm-project/polly/lib/External/isl/test_inputs/codegen/cloog/
Dmxm-shared.st1 …g4, t0, t1] -> { S1[g0 + t1, i1] : (exists (e0 = floor((g1)/128), e1 = floor((128b1 - g1)/4096), e…
3 …g4, t0, t1] -> { [] : exists (e0 = floor((g0)/8), e1 = floor((-128b1 + g1)/4096), e2 = floor((8b0 …
5 …schedule: "[N, b0, b1, g0, g1, g2, g3, g4, t0, t1] -> [{ S1[i0, i1] -> [(-g1 + i1)] }, { S1[i0, i1…
6 options: "[N, b0, b1, g0, g1, g2, g3, g4, t0, t1] -> { separate[i0] }"
/external/llvm-project/llvm/test/CodeGen/SPARC/
Datomics.ll73 ; CHECK: or %g2, %o0, %g4
74 ; CHECK: cas [%o2], %g4, %g3
75 ; CHECK: cmp %g3, %g4
76 ; CHECK: mov %o5, %g4
77 ; CHECK: move %icc, 1, %g4
78 ; CHECK: cmp %g4, 0
81 ; CHECK: and %g3, %o3, %g4
82 ; CHECK: cmp %g2, %g4
84 ; CHECK: mov %g4, %g2
114 ; CHECK: or %g2, %o4, %g4
[all …]
/external/mesa3d/src/intel/tools/tests/gen9/
Dmov.asm8 mov(8) g4<1>D -1D { align1 1Q };
9 mov.nz.f0.0(8) null<1>D g4<8,8,1>D { align1 1Q };
12 mov(8) g126<1>F g4<8,8,1>D { align1 1Q };
13 mov(16) g124<1>F g4<8,8,1>D { align1 1H };
21 mov(8) g1<1>D g4<8,8,1>D { align1 2Q };
60 mov(8) g4<1>UD 0x0F /* 0F */ { align1 1Q };
63 mov.nz.f0.0(8) g4<1>F -(abs)g2<0,1,0>F { align1 1Q };
64 (+f0.0) mov(8) g4<1>F 0xbf800000F /* -1F */ { align1 1Q };
65 mov.nz.f0.0(16) g4<1>F -(abs)g2<0,1,0>F { align1 1H };
66 (+f0.0) mov(16) g4<1>F 0xbf800000F /* -1F */ { align1 1H };
[all …]
/external/igt-gpu-tools/assembler/doc/examples/
Dpacked_yuv_wm.g4a3 * X0_R is g4
23 mov (1) g4<1>F g1.8<0,1,0>UW { align1 };
24 add (1) g4.4<1>F g1.8<0,1,0>UW 1UB { align1 };
25 mov (1) g4.8<1>F g1.8<0,1,0>UW { align1 };
26 add (1) g4.12<1>F g1.8<0,1,0>UW 1UB { align1 };
33 mov (1) g4.16<1>F g1.12<0,1,0>UW { align1 };
34 add (1) g4.20<1>F g1.12<0,1,0>UW 1UB { align1 };
35 mov (1) g4.24<1>F g1.12<0,1,0>UW { align1 };
36 add (1) g4.28<1>F g1.12<0,1,0>UW 1UB { align1 };
65 add (8) g4<1>F g4<8,8,1>F -g1<0,1,0>F { align1 };
[all …]
/external/llvm-project/clang/test/Analysis/
Dgmalloc.c32 gpointer g4 = g_try_malloc0(n_bytes); in f1() local
51 gpointer g4 = g_try_malloc0(n_bytes); in f2() local
71 gpointer g4 = g_try_malloc0(n_bytes); in f3() local
90 gpointer g4 = g_try_malloc0(n_bytes); in f4() local
102 g_free(g4); in f4()
110 gpointer g4 = g_try_malloc0(n_bytes); in f5() local
122 g_free(g4); in f5()
131 gpointer g4 = g_try_malloc0(n_bytes); in f6() local
143 g_free(g4); in f6()
153 gpointer g4 = g_try_malloc0(n_bytes); in f7() local
[all …]
/external/llvm/test/CodeGen/SPARC/
Datomics.ll88 ; CHECK: or %g2, %o0, %g4
89 ; CHECK: cas [%o2], %g4, %g3
90 ; CHECK: cmp %g3, %g4
91 ; CHECK: mov %o5, %g4
92 ; CHECK: move %icc, 1, %g4
93 ; CHECK: cmp %g4, 0
96 ; CHECK: and %g3, %o3, %g4
97 ; CHECK: cmp %g2, %g4
99 ; CHECK: mov %g4, %g2
129 ; CHECK: or %g2, %o4, %g4
[all …]

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