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Searched refs:getConstrainedRegClassForOperand (Results 1 – 10 of 10) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp104 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectCOPY()
116 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectCOPY()
140 TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectCOPY()
152 TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectCOPY()
165 TRI.getConstrainedRegClassForOperand(MO, *MRI); in selectCOPY()
476 TRI.getConstrainedRegClassForOperand(MO, *MRI); in selectG_EXTRACT()
512 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectG_MERGE_VALUES()
557 TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectG_UNMERGE_VALUES()
575 const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, *MRI); in selectG_IMPLICIT_DEF()
1191 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
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DSIRegisterInfo.h267 getConstrainedRegClassForOperand(const MachineOperand &MO,
DSIRegisterInfo.cpp1815 SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO, in getConstrainedRegClassForOperand() function in SIRegisterInfo
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h272 getConstrainedRegClassForOperand(const MachineOperand &MO,
DAMDGPUInstructionSelector.cpp113 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); in constrainCopyLikeIntrin()
115 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in constrainCopyLikeIntrin()
136 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectCOPY()
148 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectCOPY()
172 TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectCOPY()
184 TRI.getConstrainedRegClassForOperand(MO, *MRI); in selectCOPY()
477 TRI.getConstrainedRegClassForOperand(I.getOperand(0), *MRI); in selectG_EXTRACT()
529 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in selectG_MERGE_VALUES()
577 TRI.getConstrainedRegClassForOperand(Dst, *MRI); in selectG_UNMERGE_VALUES()
684 const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, *MRI); in selectG_IMPLICIT_DEF()
[all …]
DSIRegisterInfo.cpp2046 SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO, in getConstrainedRegClassForOperand() function in SIRegisterInfo
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp89 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h971 getConstrainedRegClassForOperand(const MachineOperand &MO, in getConstrainedRegClassForOperand() function
/external/llvm-project/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h1025 getConstrainedRegClassForOperand(const MachineOperand &MO, in getConstrainedRegClassForOperand() function
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp103 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()