/external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
D | nv50_ir_lowering_gv100.cpp | 39 bld.mkOp3(OP_SELP, TYPE_U32, i->getDef(0), i->getSrc(0), i->getSrc(1), pred); in handleCMP() 65 bld.mkOp2(OP_MERGE, i->dType, i->getDef(0), def[0], def[1]); in handleIADD64() 80 src2 = bld.mkOp2(OP_MERGE, TYPE_U64, bld.getSSA(8), src2s[0], src2s[1])->getDef(0); in handleIMAD_HIGH() 103 bld.mkOp3(OP_SELP, i->dType, i->getDef(0), i->getSrc(0), i->getSrc(1), pred); in handleIMNMX() 113 bld.mkOp3(OP_MAD, i->dType, i->getDef(0), i->getSrc(0), i->getSrc(1), in handleIMUL() 138 bld.mkOp3(OP_LOP3_LUT, TYPE_U32, i->getDef(0), i->getSrc(0), i->getSrc(1), in handleLOP2() 146 bld.mkOp3(OP_LOP3_LUT, TYPE_U32, i->getDef(0), bld.mkImm(0), i->getSrc(0), in handleNOT() 193 i = bld.mkOp3(OP_SELP, TYPE_U32, i->getDef(0), bld.mkImm(0), met, pred); in handleSET() 227 bld.mkOp3(OP_SHF, i->dType, i->getDef(0), src0, src1, src2)->subOp = subOp; in handleShift() 235 bld.mkOp2(OP_ADD, i->dType, i->getDef(0), i->getSrc(0), i->getSrc(1)); in handleSUB() [all …]
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D | nv50_ir_lowering_nvc0.cpp | 76 bld.mkMovFromReg(i->getDef(0), i->op == OP_DIV ? 0 : 1); in handleDIV() 93 def[0] = bld.mkMovToReg(0, src[0])->getDef(0); in handleRCPRSQLib() 94 def[1] = bld.mkMovToReg(1, src[1])->getDef(0); in handleRCPRSQLib() 108 bld.mkOp2(OP_MERGE, TYPE_U64, i->getDef(0), def[0], def[1]); in handleRCPRSQLib() 128 Value *src[2], *dst[2], *def = i->getDef(0); in handleRCPRSQ() 208 Value *dst64 = lo->getDef(0); in handleShift() 587 prev->setSrc(prev->srcCount(), useVec[i].tex->getDef(0)); in insertTextureBarriers() 593 bar->setSrc(bar->srcCount(), useVec[i].tex->getDef(0)); in insertTextureBarriers() 840 if (!i->getDef(0)->refCount()) in visit() 1276 bld.mkQuadop(0x00, tex->getDef(c), 0, tex->getDef(c), zero); in handleManualTXD() [all …]
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D | nv50_ir_lowering_gm107.cpp | 181 bld.mkOp3(OP_SHFL, TYPE_F32, tex->getDef(c), tex->getDef(c), bld.mkImm(0), quad); in handleManualTXD() 188 mov = bld.mkMov(def[c][l], tex->getDef(c)); in handleManualTXD() 195 Instruction *u = bld.mkOp(OP_UNION, TYPE_U32, i->getDef(c)); in handleManualTXD() 231 insn->setSrc(0, shfl->getDef(0)); in handleDFDX() 292 bld.mkOp2(OP_DIV, TYPE_U32, suq->getDef(d), suq->getDef(d), in handleSUQ() 300 Value *dst = suq->getDef(d); in handleSUQ() 321 bld.mkOp2(OP_SHR, TYPE_U32, suq->getDef(0), suq->getDef(0), in handleSUQ() 325 bld.mkOp2(OP_SHR, TYPE_U32, suq->getDef(d), suq->getDef(d), in handleSUQ()
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D | nv50_ir_lowering_nv50.cpp | 180 bld->mkOp2(OP_UNION, mul->sType, mul->getDef(0), rr[5], rr[6]); in expandIntegerMUL() 182 bld->mkMov(mul->getDef(0), r[4]); in expandIntegerMUL() 185 bld->mkMov(mul->getDef(0), t[3]); in expandIntegerMUL() 415 i->getDef(0)->reg.size = 2; // $aX are only 16 bit in handleAddrDef() 448 arl = bld.mkOp2(OP_SHL, TYPE_U32, i->getDef(0), bld.getSSA(), bld.mkImm(0)); in handleAddrDef() 457 Value *def = mul->getDef(0); in handleMUL() 466 Value *res = cloneShallow(func, mul->getDef(0)); in handleMUL() 469 add->setSrc(0, mul->getDef(0)); in handleMUL() 586 if (insn->defExists(0) && insn->getDef(0)->reg.file == FILE_ADDRESS) in visit() 676 tid = bld.mkMov(bld.getScratch(), arg, TYPE_U32)->getDef(0); in visit() [all …]
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D | nv50_ir_peephole.cpp | 53 if (!getDef(0)->equals(getSrc(0))) in isNop() 74 if (getDef(d)->refCount() || getDef(d)->reg.data.id >= 0) in isDead() 110 if (mov->getDef(0)->reg.data.id < 0 && si && si->op != OP_PHI) { in visit() 287 if (ld->getDef(0)->refCount() == 0) in visit() 761 i->setSrc(1, bld.mkMov(bld.getSSA(type), i->getSrc(0), type)->getDef(0)); in expr() 929 mul2->def(0).replace(mul1->getDef(0), false); in tryCollapseChainedMULs() 936 mul2->def(0).replace(mul1->getDef(0), false); in tryCollapseChainedMULs() 944 if (mul2->getDef(0)->refCount() == 1 && !mul2->saturate) { in tryCollapseChainedMULs() 948 insn = (*mul2->getDef(0)->uses.begin())->getInsn(); in tryCollapseChainedMULs() 953 s2 = insn->getSrc(0) == mul1->getDef(0) ? 0 : 1; in tryCollapseChainedMULs() [all …]
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D | nv50_ir_ra.cpp | 516 LValue *tmp = new_LValue(func, phi->getDef(0)->asLValue()); in visit() 562 LValue *tmp = new_LValue(func, cal->getDef(d)->asLValue()); in visit() 568 mov->setDef(0, cal->getDef(d)); in visit() 646 bb->liveSet.clr(i->getDef(d)->id); in buildLiveSets() 652 bb->liveSet.clr(i->getDef(0)->id); in buildLiveSets() 699 bb->liveSet.clr(i->getDef(0)->id); in visit() 720 bb->liveSet.clr(i->getDef(d)->id); in visit() 721 if (i->getDef(d)->reg.data.id >= 0) // add hazard for fixed regs in visit() 722 i->getDef(d)->livei.extend(i->serial, i->serial); in visit() 1089 LValue *rep = (split ? insn->getSrc(0) : insn->getDef(0))->asLValue(); in makeCompound() [all …]
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/external/llvm/utils/TableGen/ |
D | CodeGenInstruction.cpp | 36 if (Init->getDef()->getName() != "outs") in CGIOperandList() 45 if (Init->getDef()->getName() != "ins") in CGIOperandList() 69 Record *Rec = Arg->getDef(); in CGIOperandList() 90 cast<DefInit>(MIOpInfo->getOperator())->getDef()->getName() != "ops") in CGIOperandList() 446 Record *ResultRecord = ADI ? ADI->getDef() : nullptr; in tryAliasOpMatch() 448 if (ADI && ADI->getDef() == InstOpRec) { in tryAliasOpMatch() 463 if (ADI && ADI->getDef()->isSubClassOf("RegisterOperand")) in tryAliasOpMatch() 464 ADI = ADI->getDef()->getValueAsDef("RegClass")->getDefInit(); in tryAliasOpMatch() 466 if (ADI && ADI->getDef()->isSubClassOf("RegisterClass")) { in tryAliasOpMatch() 470 .hasSubClass(&T.getRegisterClass(ADI->getDef()))) in tryAliasOpMatch() [all …]
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D | OptParserEmitter.cpp | 181 OS << getOptionName(*DI->getDef()); in EmitOptParser() 226 GroupFlags = DI->getDef()->getValueAsListInit("Flags"); in EmitOptParser() 227 OS << getOptionName(*DI->getDef()); in EmitOptParser() 234 OS << getOptionName(*DI->getDef()); in EmitOptParser() 259 << cast<DefInit>(I)->getDef()->getName(); in EmitOptParser() 263 << cast<DefInit>(I)->getDef()->getName(); in EmitOptParser()
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D | PseudoLoweringEmitter.cpp | 81 if (DI->getDef()->isSubClassOf("Register") || in addDagOperandMapping() 82 DI->getDef()->getName() == "zero_reg") { in addDagOperandMapping() 84 OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); in addDagOperandMapping() 93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) in addDagOperandMapping() 95 "Pseudo operand type '" + DI->getDef()->getName() + in addDagOperandMapping() 135 Record *Operator = OpDef->getDef(); in evaluateExpansion()
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D | CodeGenDAGPatterns.cpp | 875 Record *Def = Pred->getDef(); in getPredicateCheck() 1024 !static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef() in ApplyTypeConstraint() 1030 getValueType(static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef()); in ApplyTypeConstraint() 1237 Op = DI->getDef(); in GetNumNodeResults() 1326 return ((DI->getDef() == NDI->getDef()) in isIsomorphicTo() 1385 cast<DefInit>(Val)->getDef()->getName() == "node")) { in SubstituteFormalArguments() 1603 Rec = DI->getDef(); in getComplexPatternInfo() 1620 if (DI && DI->getDef()->isSubClassOf("Operand")) { in getNumMIResults() 1621 DagInit *MIOps = DI->getDef()->getValueAsDag("MIOperandInfo"); in getNumMIResults() 1675 if (DI && DI->getDef()->isSubClassOf(Class)) in isOperandClass() [all …]
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/external/llvm-project/llvm/utils/TableGen/ |
D | CodeGenInstruction.cpp | 35 if (Init->getDef()->getName() != "outs") in CGIOperandList() 47 if (Init->getDef()->getName() != "ins") in CGIOperandList() 76 Record *Rec = Arg->getDef(); in CGIOperandList() 98 cast<DefInit>(MIOpInfo->getOperator())->getDef()->getName() != "ops") in CGIOperandList() 528 return Constraint->getDef()->isSubClassOf("TypedOperand") && in isOperandImpl() 529 Constraint->getDef()->getValueAsBit(PropertyName); in isOperandImpl() 546 Record *ResultRecord = ADI ? ADI->getDef() : nullptr; in tryAliasOpMatch() 548 if (ADI && ADI->getDef() == InstOpRec) { in tryAliasOpMatch() 564 if (ADI && ADI->getDef()->isSubClassOf("RegisterOperand")) in tryAliasOpMatch() 565 ADI = ADI->getDef()->getValueAsDef("RegClass")->getDefInit(); in tryAliasOpMatch() [all …]
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D | PseudoLoweringEmitter.cpp | 80 if (DI->getDef()->isSubClassOf("Register") || in addDagOperandMapping() 81 DI->getDef()->getName() == "zero_reg") { in addDagOperandMapping() 83 OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); in addDagOperandMapping() 93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) { in addDagOperandMapping() 95 "', operand type '" + DI->getDef()->getName() + in addDagOperandMapping() 98 PrintFatalNote(DI->getDef(), in addDagOperandMapping() 141 Record *Operator = OpDef->getDef(); in evaluateExpansion()
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D | RegisterBankEmitter.cpp | 60 const Record &getDef() const { return TheDef; } in getDef() function in __anonaeb9d7660111::RegisterBank 67 for (const auto *RCDef : getDef().getValueAsListOfDefs("RegisterClasses")) in getExplicitlySpecifiedRegisterClasses() 311 PrintWarning(Bank.getDef().getLoc(), "Register bank names should be " in run() 314 PrintNote(Bank.getDef().getLoc(), "RegisterBank was declared here"); in run() 315 PrintNote(Class.getDef()->getLoc(), "RegisterClass was declared here"); in run()
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D | RISCVCompressInstEmitter.cpp | 209 if (DI->getDef()->isSubClassOf("Register")) { in addDagOperandMapping() 211 if (!validateRegister(DI->getDef(), Inst.Operands[i].Rec)) in addDagOperandMapping() 214 "'Register: '" + DI->getDef()->getName() + in addDagOperandMapping() 218 OperandMap[i].Data.Reg = DI->getDef(); in addDagOperandMapping() 225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping() 229 DI->getDef()->getName() + in addDagOperandMapping() 292 return Type1->getDef() == Type2->getDef(); in validateArgsTypes() 501 !cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature")) in getReqFeatures() 504 AnyOfSet.insert({IsNot, cast<DefInit>(Arg)->getDef()->getName()}); in getReqFeatures() 506 FeaturesSet.insert({IsNot, cast<DefInit>(Arg)->getDef()->getName()}); in getReqFeatures()
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D | OptParserEmitter.cpp | 280 OS << getOptionName(*DI->getDef()); in EmitOptParser() 324 GroupFlags = DI->getDef()->getValueAsListInit("Flags"); in EmitOptParser() 325 OS << getOptionName(*DI->getDef()); in EmitOptParser() 332 OS << getOptionName(*DI->getDef()); in EmitOptParser() 356 OS << (NumFlags++ ? " | " : "") << cast<DefInit>(I)->getDef()->getName(); in EmitOptParser() 360 << cast<DefInit>(I)->getDef()->getName(); in EmitOptParser()
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/external/llvm-project/mlir/lib/TableGen/ |
D | Attribute.cpp | 49 Attribute::Attribute(const DefInit *init) : Attribute(init->getDef()) {} in Attribute() 81 return Type(defInit->getDef()); in getValueType() 136 return Dialect(init->getDef()); in getDialect() 141 ConstantAttr::ConstantAttr(const DefInit *init) : def(init->getDef()) { in ConstantAttr() 160 : EnumAttrCase(init->getDef()) {} in EnumAttrCase() 172 const llvm::Record &EnumAttrCase::getDef() const { return *def; } in getDef() function in EnumAttrCase 181 EnumAttr::EnumAttr(const llvm::DefInit *init) : EnumAttr(init->getDef()) {} in EnumAttr() 243 : StructFieldAttr(init->getDef()) {} in StructFieldAttr() 260 : StructAttr(init->getDef()) {} in StructAttr()
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D | Operator.cpp | 91 const llvm::Record &Operator::getDef() const { return def; } in getDef() function in Operator 117 cast<DefInit>(def.getValueAsDag("results")->getArg(index))->getDef(); in getResultDecorators() 155 cast<DefInit>(def.getValueAsDag("arguments")->getArg(index))->getDef(); in getArgDecorators() 265 auto *inferTrait = recordKeeper.getDef(inferTypeOpInterface); in populateTypeInferenceInfo() 318 const llvm::Record &def = trait.getDef(); in populateTypeInferenceInfo() 327 if (&opTrait->getDef() == inferTrait) in populateTypeInferenceInfo() 373 Record *argDef = argDefInit->getDef(); in populateOpStructure() 422 Record *argDef = dyn_cast<DefInit>(argumentValues->getArg(i))->getDef(); in populateOpStructure() 440 if (!outsOp || outsOp->getDef()->getName() != "outs") { in populateOpStructure() 452 auto *resultDef = resultInit->getDef(); in populateOpStructure() [all …]
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D | TypeDef.cpp | 26 return Dialect(dialectDef->getDef()); in getDialect() 114 llvm::RecordVal *code = typeParameter->getDef()->getValue("allocator"); in getAllocator() 123 typeParameter->getDef()->getLoc(), in getAllocator() 136 return typeParameter->getDef()->getValueAsString("cppType"); in getCppType() 144 const auto *desc = typeParameter->getDef()->getValue("description"); in getDescription() 155 const auto *syntax = typeParameter->getDef()->getValue("syntax"); in getSyntax()
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D | Interfaces.cpp | 79 methods.emplace_back(cast<llvm::DefInit>(init)->getDef()); in Interface() 127 return interface->getDef().isSubClassOf("AttrInterface"); in classof() 135 return interface->getDef().isSubClassOf("OpInterface"); in classof() 143 return interface->getDef().isSubClassOf("TypeInterface"); in classof()
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D | SideEffects.cpp | 40 return var->getDef().isSubClassOf("SideEffect"); in classof() 57 return t->getDef().isSubClassOf("SideEffectsTraitBase"); in classof()
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D | Pattern.cpp | 64 return Constraint(cast<llvm::DefInit>(def)->getDef()); in getAsConstraint() 83 return cast<llvm::DefInit>(def)->getDef()->getValueAsString("expression"); in getNativeCodeTemplate() 92 return defInit->getDef()->isSubClassOf(superclass); in isSubClassOf() 107 return defInit->getDef()->isSubClassOf("NativeCodeCall"); in isNativeCodeCall() 118 ->getDef() in getNativeCodeTemplate() 125 llvm::Record *opDef = cast<llvm::DefInit>(node->getOperator())->getDef(); in getDialectOp() 162 auto *dagOpDef = cast<llvm::DefInit>(node->getOperator())->getDef(); in isReplaceWithValue() 167 auto *dagOpDef = cast<llvm::DefInit>(node->getOperator())->getDef(); in isLocationDirective() 584 ret.emplace_back(cast<llvm::DefInit>(dagInit->getOperator())->getDef(), in getConstraints()
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/external/tensorflow/tensorflow/compiler/mlir/lite/ |
D | converter_gen.cc | 116 if (arg_def->getDef()->isSubClassOf(attr_type)) { in EmitOptionBuilders() 285 if (!arg_def->getDef()->isSubClassOf(attr_type)) { in EmitOperandNumbers() 287 if (arg_def->getDef()->isSubClassOf(optional_tensor)) { in EmitOperandNumbers() 379 if (arg_def->getDef()->isSubClassOf(attr_type)) { in EmitBuiltinOptionsToAttributes() 447 auto *val = definit->getDef()->getValue("tflRuntimeTypePredicate"); in GenOperandResultVerifier() 459 definit->getDef()->getValueAsString("tflRuntimeTypeDescription"); in GenOperandResultVerifier() 524 if (!trait.getDef().isSubClassOf("GenInternalOpTrait")) { in RuntimeVerifierWriterMain() 527 if (trait.getDef().getValueAsString("trait") != in RuntimeVerifierWriterMain() 532 auto *val = trait.getDef().getValue("tflRuntimePredicate"); in RuntimeVerifierWriterMain() 535 auto desc = trait.getDef().getValueAsString("tflRuntimeDescription"); in RuntimeVerifierWriterMain()
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/external/clang/utils/TableGen/ |
D | ClangSACheckersEmitter.cpp | 33 return isHidden(*DI->getDef()); in isHidden() 47 name = getPackageFullName(DI->getDef()); in getParentPackageFullName() 135 package = DI->getDef(); in EmitClangSACheckers() 156 Record *parentPackage = DI->getDef(); in EmitClangSACheckers() 162 recordGroupMap[DI->getDef()]->Checkers.insert(R); in EmitClangSACheckers() 169 addPackageToCheckerGroup(packages[i], DI->getDef(), recordGroupMap); in EmitClangSACheckers() 210 OS << groupToSortIndex[DI->getDef()] << ", "; in EmitClangSACheckers() 238 OS << groupToSortIndex[DI->getDef()] << ", "; in EmitClangSACheckers()
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/external/llvm-project/mlir/tools/mlir-tblgen/ |
D | PassGen.cpp | 108 StringRef defName = pass.getDef()->getName(); in emitPassDecl() 169 os << llvm::formatv(passRegistrationCode, pass.getDef()->getName(), in emitRegistration() 176 os << " register" << pass.getDef()->getName() << "Pass();\n"; in emitRegistration()
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D | PassCAPIGen.cpp | 65 StringRef defName = pass.getDef()->getName(); in emitCAPIHeader() 99 StringRef defName = pass.getDef()->getName(); in emitCAPIImpl()
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