| /external/llvm-project/llvm/unittests/CodeGen/ |
| D | ScalableVectorMVTsTest.cpp | 155 EXPECT_LT(v2i32.getFixedSizeInBits(), v2i64.getFixedSizeInBits()); in TEST()
156 EXPECT_LE(v4i32.getFixedSizeInBits(), v2i64.getFixedSizeInBits()); in TEST()
157 EXPECT_GT(v4i32.getFixedSizeInBits(), v2i32.getFixedSizeInBits()); in TEST()
158 EXPECT_GE(v2i64.getFixedSizeInBits(), v4i32.getFixedSizeInBits()); in TEST()
166 EXPECT_EQ(v4i32.getFixedSizeInBits(), 128U); in TEST()
167 EXPECT_EQ(v2i64.getFixedSizeInBits(), 128U); in TEST()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | CallLowering.cpp | 384 if (OrigVT.getFixedSizeInBits() >= VAVT.getFixedSizeInBits() || in handleAssignments()
420 if (VAVT.getFixedSizeInBits() < OrigVT.getFixedSizeInBits()) { in handleAssignments()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 338 uint64_t ValSize = VA.getValVT().getFixedSizeInBits(); in assignValueToReg()
339 uint64_t LocSize = VA.getLocVT().getFixedSizeInBits(); in assignValueToReg()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TypePromotion.cpp | 985 if (RegisterBitWidth < PromotedVT.getFixedSizeInBits()) { in runOnFunction()
991 MadeChange |= TryToPromote(I, PromotedVT.getFixedSizeInBits()); in runOnFunction()
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| D | TargetLoweringBase.cpp | 725 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions()
1415 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() && in computeRegisterProperties()
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.h | 341 uint64_t getFixedSizeInBits() const { in getFixedSizeInBits() function
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| D | SelectionDAGNodes.h | 183 return getValueType().getScalarType().getFixedSizeInBits();
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 350 if (VT.getFixedSizeInBits() >= RegisterVT.getFixedSizeInBits()) in determineLocInfo()
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| D | MipsISelLowering.cpp | 137 NumIntermediates = VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits() in getVectorTypeBreakdownForCallingConv()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 489 if (DstVT.getFixedSizeInBits() < SrcVT.getFixedSizeInBits()) in getExtractWithExtendCost()
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| D | AArch64ISelLowering.cpp | 3112 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorFP_TO_INT()
3113 uint64_t InVTSize = InVT.getFixedSizeInBits(); in LowerVectorFP_TO_INT()
3184 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorINT_TO_FP()
3185 uint64_t InVTSize = InVT.getFixedSizeInBits(); in LowerVectorINT_TO_FP()
4374 if (VT.getFixedSizeInBits() <= 128) in useSVEForFixedLengthVectorVT()
4378 if (VT.getFixedSizeInBits() > Subtarget->getMinSVEVectorSizeInBits()) in useSVEForFixedLengthVectorVT()
5381 OpSize = VA.getLocVT().getFixedSizeInBits(); in LowerCall()
6171 cast<VTSDNode>(Val.getOperand(1))->getVT().getFixedSizeInBits() - in lookThroughSignExtension()
6176 Val.getOperand(0)->getValueType(0).getFixedSizeInBits() - 1}; in lookThroughSignExtension()
7543 if (VT.getFixedSizeInBits() == 64) in getRegForInlineAsmConstraint()
[all …]
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | IntrinsicEmitter.cpp | 257 unsigned BitWidth = MVT(VT).getFixedSizeInBits(); in EncodeFixedValueType()
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| D | CodeGenDAGPatterns.cpp | 2393 unsigned Size = MVT(VT).getFixedSizeInBits(); in ApplyTypeConstraints()
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| /external/llvm-project/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 1400 return (VT1.getFixedSizeInBits() > VT2.getFixedSizeInBits()); in isTruncateFree()
|
| /external/llvm-project/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 986 uint64_t getFixedSizeInBits() const { in getFixedSizeInBits() function
|
| /external/llvm-project/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 2593 Ins[InsIdx].VT.getFixedSizeInBits() > in LowerFormalArguments()
2594 LoadVT.getFixedSizeInBits()) { in LowerFormalArguments()
4568 if (OrigVT.getFixedSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
4574 if (OrigVT.getFixedSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 7292 unsigned NumBits = NewStoredVT.getFixedSizeInBits(); in expandUnalignedStore()
7350 APInt(AddrVT.getFixedSizeInBits(), in IncrementMemoryAddress()
7369 APInt(IdxVT.getFixedSizeInBits(), in clampDynamicVectorIndex()
7398 unsigned EltSize = EltVT.getFixedSizeInBits() / 8; // FIXME: should be ABI size. in getVectorElementPointer()
7399 assert(EltSize * 8 == EltVT.getFixedSizeInBits() && in getVectorElementPointer()
8030 unsigned LoSize = VT.getFixedSizeInBits(); in expandMULO()
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| D | LegalizeVectorTypes.cpp | 1569 EltVT.getFixedSizeInBits() / 8)); in SplitVecRes_INSERT_VECTOR_ELT()
2370 commonAlignment(SmallestAlign, EltVT.getFixedSizeInBits() / 8)); in SplitVecOp_EXTRACT_VECTOR_ELT()
4975 if (RetVT.getFixedSizeInBits() < MemVTWidth || MemVT == WidenVT) in FindMemType()
5240 unsigned ValEltWidth = ValEltVT.getFixedSizeInBits(); in GenWidenVectorStores()
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| D | SelectionDAGBuilder.cpp | 672 uint64_t ValueSize = ValueVT.getFixedSizeInBits(); in getCopyToPartsVector()
673 assert(PartVT.getFixedSizeInBits() > ValueSize && in getCopyToPartsVector()
6354 if (PtrTy.getFixedSizeInBits() < ResTy.getFixedSizeInBits()) in visitIntrinsicCall()
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| D | DAGCombiner.cpp | 5783 LHS.getOperand(0).getValueType().getFixedSizeInBits())) in visitAND()
15278 DAG.getConstant(APInt::getLowBitsSet(STType.getFixedSizeInBits(), in ForwardStoreValueToDirectLoad()
17610 unsigned STBitSize = ST->getMemoryVT().getFixedSizeInBits(); in visitSTORE()
17611 unsigned ChainBitSize = ST1->getMemoryVT().getFixedSizeInBits(); in visitSTORE()
18708 uint64_t VTSize = VT.getFixedSizeInBits(); in createBuildVecShuffle()
18709 uint64_t InVT1Size = InVT1.getFixedSizeInBits(); in createBuildVecShuffle()
18710 uint64_t InVT2Size = InVT2.getFixedSizeInBits(); in createBuildVecShuffle()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 7080 if (ValVT.getFixedSizeInBits() < RegVT.getFixedSizeInBits()) in CC_AIX()
7185 assert(ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits()); in truncateScalarIntegerArg()
7391 (ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits())) { in LowerFormalArguments_AIX()
7684 else if (Arg.getValueType().getFixedSizeInBits() < in LowerCall_AIX()
7685 LocVT.getFixedSizeInBits()) in LowerCall_AIX()
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| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2545 std::min(PtrVT.getFixedSizeInBits(), VT.getFixedSizeInBits()) / 8); in LowerVAARG()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 3216 if (VT.getFixedSizeInBits() <= EltVT.getFixedSizeInBits()) { in performTruncateCombine()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 249 int ElemWidth = ElemTy.getFixedSizeInBits(); in initializeHVXLowering()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 4547 if (VA.getLocVT().getFixedSizeInBits() > in MatchingStackOffset()
5896 assert(Vec.getValueSizeInBits().getFixedSize() < VT.getFixedSizeInBits() && in widenSubVector()
7530 return SubVT.getFixedSizeInBits() < in getFauxShuffleMask()
22703 if (VT.getFixedSizeInBits() > in LowerVSETCC()
22704 Op.getSimpleValueType().getFixedSizeInBits()) { in LowerVSETCC()
23677 assert(SVT.getFixedSizeInBits() > InSVT.getFixedSizeInBits()); in LowerEXTEND_VECTOR_INREG()
36708 VT.getFixedSizeInBits()) { in combineTargetShuffle()
44338 if (InScalarVT.getFixedSizeInBits() <= ScalarVT.getFixedSizeInBits()) in detectAVGPattern()
49013 SubVecVT.getFixedSizeInBits()) in combineInsertSubvector()
49639 User->getValueSizeInBits(0).getFixedSize() > VT.getFixedSizeInBits()) { in combineVBROADCAST_LOAD()
|