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Searched refs:getNumNativeRegUnits (Results 1 – 4 of 4) sorted by relevance

/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp218 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
226 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() in EmitRegUnitPressure()
230 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
323 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() in EmitRegUnitPressure()
327 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
970 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { in runMCDesc()
1075 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " in runMCDesc()
1440 << " " << RegBank.getNumNativeRegUnits() << ",\n" in runTargetDesc()
DCodeGenRegisters.h642 unsigned getNumNativeRegUnits() const { in getNumNativeRegUnits() function
/external/llvm-project/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp236 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
244 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() in EmitRegUnitPressure()
248 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
342 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() in EmitRegUnitPressure()
346 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
1031 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { in runMCDesc()
1126 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " in runMCDesc()
1532 << " " << RegBank.getNumNativeRegUnits() << ",\n" in runTargetDesc()
DCodeGenRegisters.h708 unsigned getNumNativeRegUnits() const { in getNumNativeRegUnits() function