Searched refs:getRegClasses (Results 1 – 14 of 14) sorted by relevance
186 for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) { in visitRegisterBankClasses()203 BitVector BV(RegisterClassHierarchy.getRegClasses().size()); in visitRegisterBankClasses()224 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); in emitBaseClassImplementation()256 << RegisterClassHierarchy.getRegClasses().size() << ");\n"; in emitBaseClassImplementation()308 for (const auto &Class : RegisterClassHierarchy.getRegClasses()) { in run()
135 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()210 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()1042 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc()1190 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader()1226 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetDesc()1645 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { in debugDump()1664 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { in debugDump()
284 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace()348 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg()409 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()424 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
715 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses() function717 const std::list<CodeGenRegisterClass> &getRegClasses() const { in getRegClasses() function
946 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses()1009 auto &RegClasses = RegBank.getRegClasses(); in getMatchingSubClassWithSubRegs()1614 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets()1899 auto &RegClasses = getRegClasses(); in computeRegUnitSets()2354 for (const auto &RC : getRegClasses()) { in getRegClassForRegister()2395 for (const auto &RC : getRegClasses()) { in getMinimalPhysRegClass()
29 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
1216 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()
122 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()192 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()199 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()981 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc()1138 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader()1174 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetDesc()
649 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses() function651 const std::list<CodeGenRegisterClass> &getRegClasses() const { in getRegClasses() function
246 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()261 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
851 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses()1334 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets()1614 auto &RegClasses = getRegClasses(); in computeRegUnitSets()2065 for (const auto &RC : getRegClasses()) { in getRegClassForRegister()
30 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
1204 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()
72 const auto &RegisterClasses = Bank.getRegClasses();210 const auto &RegisterClasses = RegBank.getRegClasses();