| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 299 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) { in getCommonSuperRegClass()
307 unsigned MinSize = getRegSizeInBits(*RCA); in getCommonSuperRegClass()
315 if (!RC || getRegSizeInBits(*RC) < MinSize) in getCommonSuperRegClass()
324 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC)) in getCommonSuperRegClass()
333 if (getRegSizeInBits(*BestRC) == MinSize) in getCommonSuperRegClass()
472 unsigned TargetRegisterInfo::getRegSizeInBits(unsigned Reg, in getRegSizeInBits() function in TargetRegisterInfo
491 return getRegSizeInBits(*RC); in getRegSizeInBits()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 319 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) { in getCommonSuperRegClass()
327 unsigned MinSize = getRegSizeInBits(*RCA); in getCommonSuperRegClass()
335 if (!RC || getRegSizeInBits(*RC) < MinSize) in getCommonSuperRegClass()
344 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC)) in getCommonSuperRegClass()
353 if (getRegSizeInBits(*BestRC) == MinSize) in getCommonSuperRegClass()
490 TargetRegisterInfo::getRegSizeInBits(Register Reg, in getRegSizeInBits() function in TargetRegisterInfo
509 return getRegSizeInBits(*RC); in getRegSizeInBits()
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| D | ImplicitNullChecks.cpp | 389 unsigned PointerRegSizeInBits = TRI->getRegSizeInBits(PointerReg, MRI); in isSuitableMemoryOp()
393 TRI->getRegSizeInBits(BaseReg, MRI) != PointerRegSizeInBits) || in isSuitableMemoryOp()
395 TRI->getRegSizeInBits(ScaledReg, MRI) != PointerRegSizeInBits)) in isSuitableMemoryOp()
426 int32_t RegSizeInBits = TRI->getRegSizeInBits(RegUsedInAddr, MRI); in isSuitableMemoryOp()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 135 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
142 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
149 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
156 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
170 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 130 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
137 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
144 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
151 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
165 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
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| /external/llvm-project/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 351 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) in shouldCoalesce()
358 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0); in shouldCoalesce()
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| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 350 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) in shouldCoalesce()
357 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0); in shouldCoalesce()
|
| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
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| D | InlineAsmLowering.cpp | 251 unsigned SrcSize = TRI->getRegSizeInBits(Src, *MRI); in buildAnyextOrCopy()
252 unsigned DstSize = TRI->getRegSizeInBits(Dst, *MRI); in buildAnyextOrCopy()
624 unsigned SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI); in lowerInlineAsm()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegPressure.cpp | 91 (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) : in getRegKind()
93 (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) : in getRegKind()
94 (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE); in getRegKind()
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| D | SIRegisterInfo.cpp | 1274 unsigned Size = getRegSizeInBits(*RC); in hasVGPRs()
1301 unsigned Size = getRegSizeInBits(*RC); in hasAGPRs()
1327 switch (getRegSizeInBits(*SRC)) { in getEquivalentVGPRClass()
1353 switch (getRegSizeInBits(*SRC)) { in getEquivalentAGPRClass()
1371 switch (getRegSizeInBits(*VRC)) { in getEquivalentSGPRClass()
1708 unsigned SrcSize = getRegSizeInBits(*SrcRC); in shouldCoalesce()
1709 unsigned DstSize = getRegSizeInBits(*DstRC); in shouldCoalesce()
1710 unsigned NewSize = getRegSizeInBits(*NewRC); in shouldCoalesce()
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| D | SIAddIMGInit.cpp | 127 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in runOnMachineFunction()
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| D | GCNRegBankReassign.cpp | 282 unsigned Size = TRI->getRegSizeInBits(*RC); in getPhysRegBank()
309 unsigned Size = TRI->getRegSizeInBits(*RC) / 32; in getRegBankMask()
446 unsigned Size = TRI->getRegSizeInBits(*RC); in isReassignable()
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| D | SILowerI1Copies.cpp | 106 TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) == in isLaneMaskReg()
497 unsigned Size = TRI.getRegSizeInBits(Reg, MRI); in isVRegCompatibleReg()
703 assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32); in lowerCopiesToI1()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNRegPressure.cpp | 96 (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) : in getRegKind()
98 (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) : in getRegKind()
99 (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE); in getRegKind()
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| D | GCNRegBankReassign.cpp | 306 unsigned Size = TRI->getRegSizeInBits(*RC); in getPhysRegBank()
313 if (TRI->getRegSizeInBits(*SubRC) > 32) in getPhysRegBank()
343 unsigned Size = TRI->getRegSizeInBits(*RC); in getRegBankMask()
496 unsigned Size = TRI->getRegSizeInBits(*RC); in isReassignable()
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| D | SIRegisterInfo.cpp | 1796 unsigned Size = getRegSizeInBits(*RC); in hasVGPRs()
1810 unsigned Size = getRegSizeInBits(*RC); in hasAGPRs()
1823 unsigned Size = getRegSizeInBits(*SRC); in getEquivalentVGPRClass()
1831 unsigned Size = getRegSizeInBits(*SRC); in getEquivalentAGPRClass()
1839 unsigned Size = getRegSizeInBits(*VRC); in getEquivalentSGPRClass()
1964 unsigned SrcSize = getRegSizeInBits(*SrcRC); in shouldCoalesce()
1965 unsigned DstSize = getRegSizeInBits(*DstRC); in shouldCoalesce()
1966 unsigned NewSize = getRegSizeInBits(*NewRC); in shouldCoalesce()
2131 assert(getRegSizeInBits(*getPhysRegClass(Reg)) <= 32); in get32BitRegister()
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| D | SIAddIMGInit.cpp | 122 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in runOnMachineFunction()
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| D | SILowerI1Copies.cpp | 105 TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) == in isLaneMaskReg()
501 unsigned Size = TRI.getRegSizeInBits(Reg, MRI); in isVRegCompatibleReg()
706 assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32); in lowerCopiesToI1()
|
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRAsmPrinter.cpp | 112 unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8; in PrintAsmOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRAsmPrinter.cpp | 112 unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8; in PrintAsmOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 851 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
852 getRegSizeInBits(*SrcRC) < 256) in shouldCoalesce()
|