| /external/OpenCSD/decoder/tests/snapshot_parser_lib/source/ |
| D | ss_to_dcdtree.cpp | 273 …configOK = getRegisters(devSrc->regDefs,sizeof(regs_to_access)/sizeof(regs_to_access_t), regs_to_a… in createETMv4Decoder()
320 …configOK = getRegisters(devSrc->regDefs, sizeof(regs_to_access) / sizeof(regs_to_access_t), regs_t… in createETEDecoder()
364 …configOK = getRegisters(devSrc->regDefs,sizeof(regs_to_access)/sizeof(regs_to_access_t), regs_to_a… in createETMv3Decoder()
402 …configOK = getRegisters(devSrc->regDefs,sizeof(regs_to_access)/sizeof(regs_to_access_t), regs_to_a… in createPTMDecoder()
454 …configOK = getRegisters(devSrc->regDefs,sizeof(regs_to_access)/sizeof(regs_to_access_t), regs_to_a… in createSTMDecoder()
474 bool CreateDcdTreeFromSnapShot::getRegisters(std::map<std::string, std::string, Util::CaseInsensiti… in getRegisters() function in CreateDcdTreeFromSnapShot
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUPALMetadata.cpp | 161 auto Regs = getRegisters(); in getRegister()
180 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)]; in setRegister()
555 auto Regs = getRegisters(); in toString()
606 auto Registers = getRegisters(); in toLegacyBlob()
665 msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() { in getRegisters() function in AMDGPUPALMetadata
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| D | AMDGPUPALMetadata.h | 121 msgpack::MapDocNode getRegisters();
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| /external/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUPALMetadata.cpp | 164 auto Regs = getRegisters(); in getRegister()
183 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)]; in setRegister()
616 auto Regs = getRegisters(); in toString()
667 auto Registers = getRegisters(); in toLegacyBlob()
726 msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() { in getRegisters() function in AMDGPUPALMetadata
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| D | AMDGPUPALMetadata.h | 125 msgpack::MapDocNode getRegisters();
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| /external/llvm-project/openmp/tools/analyzer/ |
| D | analyzer.py | 18 def getRegisters(usages): function
37 …info["Usage"] = {"Registers" : getRegisters(usages), "Shared" : getSharedMem(usages), "Kernel" : g…
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| /external/OpenCSD/decoder/tests/snapshot_parser_lib/include/ |
| D | ss_to_dcdtree.h | 84 …bool getRegisters(std::map<std::string, std::string, Util::CaseInsensitiveLess> ®Defs, int numR…
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 104 const auto &Registers = Bank.getRegisters(); in runEnums()
884 const auto &Regs = RegBank.getRegisters(); in runMCDesc()
1451 const auto &Regs = RegBank.getRegisters(); in runTargetDesc()
1683 for (const CodeGenRegister &R : RegBank.getRegisters()) { in debugDump()
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| D | CodeGenRegisters.h | 651 const std::deque<CodeGenRegister> &getRegisters() const { in getRegisters() function
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| D | AsmMatcherEmitter.cpp | 1215 const auto &Registers = Target.getRegBank().getRegisters(); in buildRegisterClasses()
2599 const auto &Regs = Target.getRegBank().getRegisters(); in emitMatchRegisterName()
2624 const auto &Regs = Target.getRegBank().getRegisters(); in emitMatchRegisterAltName()
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| D | AsmWriterEmitter.cpp | 609 const auto &Registers = Target.getRegBank().getRegisters(); in EmitGetRegisterName()
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| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 90 const auto &Registers = Bank.getRegisters(); in runEnums()
822 const auto &Regs = RegBank.getRegisters(); in runMCDesc()
1361 const auto &Regs = RegBank.getRegisters(); in runTargetDesc()
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| D | CodeGenRegisters.h | 592 const std::deque<CodeGenRegister> &getRegisters() { return Registers; } in getRegisters() function
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| D | AsmMatcherEmitter.cpp | 1203 const auto &Registers = Target.getRegBank().getRegisters(); in buildRegisterClasses()
2337 const auto &Regs = Target.getRegBank().getRegisters(); in emitMatchRegisterName()
2360 const auto &Regs = Target.getRegBank().getRegisters(); in emitMatchRegisterAltName()
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| D | AsmWriterEmitter.cpp | 550 const auto &Registers = Target.getRegBank().getRegisters(); in EmitGetRegisterName()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAsmPrinter.cpp | 653 for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) { in analyzeResourceUsage()
662 for (MCPhysReg Reg : reverse(AMDGPU::AGPR_32RegClass.getRegisters())) { in analyzeResourceUsage()
673 for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) { in analyzeResourceUsage()
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| D | SIMachineFunctionInfo.cpp | 344 auto Regs = RC.getRegisters(); in allocateVGPRSpillToAGPR()
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| D | GCNRegBankReassign.cpp | 598 for (unsigned Reg : RC->getRegisters()) { in scavengeReg()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAsmPrinter.cpp | 679 for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) { in analyzeResourceUsage()
688 for (MCPhysReg Reg : reverse(AMDGPU::AGPR_32RegClass.getRegisters())) { in analyzeResourceUsage()
699 for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) { in analyzeResourceUsage()
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| D | SIMachineFunctionInfo.cpp | 390 auto Regs = RC.getRegisters(); in allocateVGPRSpillToAGPR()
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| D | GCNRegBankReassign.cpp | 661 for (MCRegister Reg : RC->getRegisters()) { in scavengeReg()
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| /external/capstone/contrib/sysz_update/ |
| D | 0005-capstone-generate-GenAsmWriter.inc.patch | 136 const auto &Registers = Target.getRegBank().getRegisters();
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| D | 0001-capstone-generate-GenRegisterInfo.inc.patch | 121 const auto &Regs = RegBank.getRegisters();
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 78 getRegisters() const { in getRegisters() function
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 79 getRegisters() const { in getRegisters() function
|