| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 13 class getSubRegs<int size> {
238 def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">;
241 def SGPR_96Regs : SIRegisterTuples<getSubRegs<3>.ret, SGPR_32, 105, 3, 3, "s">;
244 def SGPR_128Regs : SIRegisterTuples<getSubRegs<4>.ret, SGPR_32, 105, 4, 4, "s">;
247 def SGPR_160Regs : SIRegisterTuples<getSubRegs<5>.ret, SGPR_32, 105, 4, 5, "s">;
250 def SGPR_256Regs : SIRegisterTuples<getSubRegs<8>.ret, SGPR_32, 105, 4, 8, "s">;
253 def SGPR_512Regs : SIRegisterTuples<getSubRegs<16>.ret, SGPR_32, 105, 4, 16, "s">;
256 def SGPR_1024Regs : SIRegisterTuples<getSubRegs<32>.ret, SGPR_32, 105, 4, 32, "s">;
265 def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">;
268 def TTMP_128Regs : SIRegisterTuples<getSubRegs<4>.ret, TTMP_32, 15, 4, 4, "ttmp">;
[all …]
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 55 class getSubRegs<int size> {
342 def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">;
345 def SGPR_96Regs : SIRegisterTuples<getSubRegs<3>.ret, SGPR_32, 105, 3, 3, "s">;
348 def SGPR_128Regs : SIRegisterTuples<getSubRegs<4>.ret, SGPR_32, 105, 4, 4, "s">;
351 def SGPR_160Regs : SIRegisterTuples<getSubRegs<5>.ret, SGPR_32, 105, 4, 5, "s">;
354 def SGPR_192Regs : SIRegisterTuples<getSubRegs<6>.ret, SGPR_32, 105, 4, 6, "s">;
357 def SGPR_256Regs : SIRegisterTuples<getSubRegs<8>.ret, SGPR_32, 105, 4, 8, "s">;
360 def SGPR_512Regs : SIRegisterTuples<getSubRegs<16>.ret, SGPR_32, 105, 4, 16, "s">;
363 def SGPR_1024Regs : SIRegisterTuples<getSubRegs<32>.ret, SGPR_32, 105, 4, 32, "s">;
378 def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">;
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenMux.cpp | 89 void getSubRegs(unsigned Reg, BitVector &SRs) const;
108 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { in getSubRegs() function in HexagonGenMux
116 getSubRegs(Reg, Set); in expandReg()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonGenMux.cpp | 127 void getSubRegs(unsigned Reg, BitVector &SRs) const;
146 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { in getSubRegs() function in HexagonGenMux
153 getSubRegs(Reg, Set); in expandReg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonGenMux.cpp | 127 void getSubRegs(unsigned Reg, BitVector &SRs) const;
146 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { in getSubRegs() function in HexagonGenMux
153 getSubRegs(Reg, Set); in expandReg()
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1188 for (auto P : Reg.getSubRegs()) { in CodeGenRegBank()
1348 const CodeGenRegister::SubRegMap &SM = R.getSubRegs(); in computeComposites()
1400 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs(); in computeComposites()
1408 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
1732 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); in normalizeWeight()
2068 const SubRegMap &SubRegs = Register.getSubRegs(); in computeRegUnitLaneMasks()
2074 if (!SubReg->getSubRegs().empty()) in computeRegUnitLaneMasks()
2198 const CodeGenRegister::SubRegMap &SRM = R->getSubRegs(); in inferSubClassWithSubReg()
2256 const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second; in inferMatchingSuperRegClass()
2426 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs(); in computeCoveredRegisters()
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| D | CodeGenRegisters.h | 183 const SubRegMap &getSubRegs() const { in getSubRegs() function
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| D | RegisterInfoEmitter.cpp | 1688 for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) { in debugDump()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1127 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs(); in computeComposites()
1135 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
1448 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); in normalizeWeight()
1787 const SubRegMap &SubRegs = Register.getSubRegs(); in computeRegUnitLaneMasks()
1793 if (SubReg->getSubRegs().size() != 0) in computeRegUnitLaneMasks()
1916 const CodeGenRegister::SubRegMap &SRM = R->getSubRegs(); in inferSubClassWithSubReg()
1970 const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second; in inferMatchingSuperRegClass()
2122 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs(); in computeCoveredRegisters()
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| D | CodeGenRegisters.h | 156 const SubRegMap &getSubRegs() const { in getSubRegs() function
|